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mcuconf.h.ftl

mcuconf.h.ftl 22 KB
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  1. [#ftl]
    2. 

  2. [#--
    3. 

  3.     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio.
    4. 

  4. 

  5.     This file is part of ChibiOS.
    6. 

  6. 

  7.     ChibiOS is free software; you can redistribute it and/or modify
    8. 

  8.     it under the terms of the GNU General Public License as published by
    9. 

  9.     the Free Software Foundation; either version 3 of the License, or
    10. 

  10.     (at your option) any later version.
    11. 

  11. 

  12.     ChibiOS is distributed in the hope that it will be useful,
    13. 

  13.     but WITHOUT ANY WARRANTY; without even the implied warranty of
    14. 

  14.     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    15. 

  15.     GNU General Public License for more details.
    16. 

  16. 

  17.     You should have received a copy of the GNU General Public License
    18. 

  18.     along with this program.  If not, see <http://www.gnu.org/licenses/>.
    19. 

  19.   --]
    20. 

  20. [@pp.dropOutputFile /]
    21. 

  21. [#import "/@lib/libutils.ftl" as utils /]
    22. 

  22. [#import "/@lib/liblicense.ftl" as license /]
    23. 

  23. [@pp.changeOutputFile name="mcuconf.h" /]
    24. 

  24. /*
    25. 

  25. [@license.EmitLicenseAsText /]
    26. 

  26. */
    27. 

  27. 

  28. #ifndef MCUCONF_H
    29. 

  29. #define MCUCONF_H
    30. 

  30. 

  31. /*
    32. 

  32.  * STM32F4xx drivers configuration.
    33. 

  33.  * The following settings override the default settings present in
    34. 

  34.  * the various device driver implementation headers.
    35. 

  35.  * Note that the settings for each driver only have effect if the whole
    36. 

  36.  * driver is enabled in halconf.h.
    37. 

  37.  *
    38. 

  38.  * IRQ priorities:
    39. 

  39.  * 15...0       Lowest...Highest.
    40. 

  40.  *
    41. 

  41.  * DMA priorities:
    42. 

  42.  * 0...3        Lowest...Highest.
    43. 

  43.  */
    44. 

  44. 

  45. #define STM32F4xx_MCUCONF
    46. 

  46. #define STM32F413_MCUCONF
    47. 

  47. 

  48. /*
    49. 

  49.  * HAL driver system settings.
    50. 

  50.  */
    51. 

  51. #define STM32_NO_INIT                       ${doc.STM32_NO_INIT!"FALSE"}
    52. 

  52. #define STM32_PVD_ENABLE                    ${doc.STM32_PVD_ENABLE!"FALSE"}
    53. 

  53. #define STM32_PLS                           ${doc.STM32_PLS!"STM32_PLS_LEV0"}
    54. 

  54. #define STM32_BKPRAM_ENABLE                 ${doc.STM32_BKPRAM_ENABLE!"FALSE"}
    55. 

  55. #define STM32_HSI_ENABLED                   ${doc.STM32_HSI_ENABLED!"TRUE"}
    56. 

  56. #define STM32_LSI_ENABLED                   ${doc.STM32_LSI_ENABLED!"TRUE"}
    57. 

  57. #define STM32_HSE_ENABLED                   ${doc.STM32_HSE_ENABLED!"TRUE"}
    58. 

  58. #define STM32_LSE_ENABLED                   ${doc.STM32_LSE_ENABLED!"FALSE"}
    59. 

  59. #define STM32_CLOCK48_REQUIRED              ${doc.STM32_CLOCK48_REQUIRED!"TRUE"}
    60. 

  60. #define STM32_SW                            ${doc.STM32_SW!"STM32_SW_PLL"}
    61. 

  61. #define STM32_PLLSRC                        ${doc.STM32_PLLSRC!"STM32_PLLSRC_HSE"}
    62. 

  62. #define STM32_PLLM_VALUE                    ${doc.STM32_PLLM_VALUE!"8"}
    63. 

  63. #define STM32_PLLN_VALUE                    ${doc.STM32_PLLN_VALUE!"384"}
    64. 

  64. #define STM32_PLLP_VALUE                    ${doc.STM32_PLLP_VALUE!"4"}
    65. 

  65. #define STM32_PLLQ_VALUE                    ${doc.STM32_PLLQ_VALUE!"8"}
    66. 

  66. #define STM32_HPRE                          ${doc.STM32_HPRE!"STM32_HPRE_DIV1"}
    67. 

  67. #define STM32_PPRE1                         ${doc.STM32_PPRE1!"STM32_PPRE1_DIV2"}
    68. 

  68. #define STM32_PPRE2                         ${doc.STM32_PPRE2!"STM32_PPRE2_DIV1"}
    69. 

  69. #define STM32_PLLI2SSRC                     ${doc.STM32_PLLI2SSRC!"STM32_PLLI2SSRC_PLLSRC"}
    70. 

  70. #define STM32_I2SCKIN_VALUE                 ${doc.STM32_I2SCKIN_VALUE!"0"}
    71. 

  71. #define STM32_PLLI2SM_VALUE                 ${doc.STM32_PLLI2SM_VALUE!"8"}
    72. 

  72. #define STM32_PLLI2SN_VALUE                 ${doc.STM32_PLLI2SN_VALUE!"192"}
    73. 

  73. #define STM32_PLLI2SR_VALUE                 ${doc.STM32_PLLI2SR_VALUE!"4"}
    74. 

  74. #define STM32_PLLI2SQ_VALUE                 ${doc.STM32_PLLI2SQ_VALUE!"4"}
    75. 

  75. #define STM32_PLLI2SDIVR_VALUE              ${doc.STM32_PLLI2SDIVR_VALUE!"1"}
    76. 

  76. #define STM32_PLLDIVR_VALUE                 ${doc.STM32_PLLDIVR_VALUE!"1"}
    77. 

  77. #define STM32_SAI1SEL                       ${doc.STM32_SAI1SEL!"STM32_SAI1SEL_OFF"}
    78. 

  78. #define STM32_SAI2SEL                       ${doc.STM32_SAI2SEL!"STM32_SAI2SEL_OFF"}
    79. 

  79. #define STM32_TIMPRE                        ${doc.STM32_TIMPRE!"STM32_TIMPRE_PCLK"}
    80. 

  80. #define STM32_CK48MSEL                      ${doc.STM32_CK48MSEL!"STM32_CK48MSEL_PLL"}
    81. 

  81. #define STM32_RTCSEL                        ${doc.STM32_RTCSEL!"STM32_RTCSEL_LSI"}
    82. 

  82. #define STM32_RTCPRE_VALUE                  ${doc.STM32_RTCPRE_VALUE!"8"}
    83. 

  83. #define STM32_MCO1SEL                       ${doc.STM32_MCO1SEL!"STM32_MCO1SEL_HSI"}
    84. 

  84. #define STM32_MCO1PRE                       ${doc.STM32_MCO1PRE!"STM32_MCO1PRE_DIV1"}
    85. 

  85. #define STM32_MCO2SEL                       ${doc.STM32_MCO2SEL!"STM32_MCO2SEL_SYSCLK"}
    86. 

  86. #define STM32_MCO2PRE                       ${doc.STM32_MCO2PRE!"STM32_MCO2PRE_DIV5"}
    87. 

  87. 

  88. /*
    89. 

  89.  * IRQ system settings.
    90. 

  90.  */
    91. 

  91. #define STM32_IRQ_EXTI0_PRIORITY            ${doc.STM32_IRQ_EXTI0_PRIORITY!"6"}
    92. 

  92. #define STM32_IRQ_EXTI1_PRIORITY            ${doc.STM32_IRQ_EXTI1_PRIORITY!"6"}
    93. 

  93. #define STM32_IRQ_EXTI2_PRIORITY            ${doc.STM32_IRQ_EXTI2_PRIORITY!"6"}
    94. 

  94. #define STM32_IRQ_EXTI3_PRIORITY            ${doc.STM32_IRQ_EXTI3_PRIORITY!"6"}
    95. 

  95. #define STM32_IRQ_EXTI4_PRIORITY            ${doc.STM32_IRQ_EXTI4_PRIORITY!"6"}
    96. 

  96. #define STM32_IRQ_EXTI5_9_PRIORITY          ${doc.STM32_IRQ_EXTI5_9_PRIORITY!"6"}
    97. 

  97. #define STM32_IRQ_EXTI10_15_PRIORITY        ${doc.STM32_IRQ_EXTI10_15_PRIORITY!"6"}
    98. 

  98. #define STM32_IRQ_EXTI16_PRIORITY           ${doc.STM32_IRQ_EXTI16_PRIORITY!"6"}
    99. 

  99. #define STM32_IRQ_EXTI17_PRIORITY           ${doc.STM32_IRQ_EXTI17_PRIORITY!"15"}
    100. 

  100. #define STM32_IRQ_EXTI18_PRIORITY           ${doc.STM32_IRQ_EXTI18_PRIORITY!"6"}
    101. 

  101. #define STM32_IRQ_EXTI19_PRIORITY           ${doc.STM32_IRQ_EXTI19_PRIORITY!"6"}
    102. 

  102. #define STM32_IRQ_EXTI20_PRIORITY           ${doc.STM32_IRQ_EXTI20_PRIORITY!"6"}
    103. 

  103. #define STM32_IRQ_EXTI21_PRIORITY           ${doc.STM32_IRQ_EXTI21_PRIORITY!"15"}
    104. 

  104. #define STM32_IRQ_EXTI22_PRIORITY           ${doc.STM32_IRQ_EXTI22_PRIORITY!"15"}
    105. 

  105. 

  106. /*
    107. 

  107.  * ADC driver system settings.
    108. 

  108.  */
    109. 

  109. #define STM32_ADC_ADCPRE                    ${doc.STM32_ADC_ADCPRE!"ADC_CCR_ADCPRE_DIV4"}
    110. 

  110. #define STM32_ADC_USE_ADC1                  ${doc.STM32_ADC_USE_ADC1!"FALSE"}
    111. 

  111. #define STM32_ADC_ADC1_DMA_STREAM           ${doc.STM32_ADC_ADC1_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
    112. 

  112. #define STM32_ADC_ADC1_DMA_PRIORITY         ${doc.STM32_ADC_ADC1_DMA_PRIORITY!"2"}
    113. 

  113. #define STM32_ADC_IRQ_PRIORITY              ${doc.STM32_ADC_IRQ_PRIORITY!"6"}
    114. 

  114. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     ${doc.STM32_ADC_ADC1_DMA_IRQ_PRIORITY!"6"}
    115. 

  115. 

  116. /*
    117. 

  117.  * CAN driver system settings.
    118. 

  118.  */
    119. 

  119. #define STM32_CAN_USE_CAN1                  ${doc.STM32_CAN_USE_CAN1!"FALSE"}
    120. 

  120. #define STM32_CAN_USE_CAN2                  ${doc.STM32_CAN_USE_CAN2!"FALSE"}
    121. 

  121. #define STM32_CAN_USE_CAN3                  ${doc.STM32_CAN_USE_CAN3!"FALSE"}
    122. 

  122. #define STM32_CAN_CAN1_IRQ_PRIORITY         ${doc.STM32_CAN_CAN1_IRQ_PRIORITY!"11"}
    123. 

  123. #define STM32_CAN_CAN2_IRQ_PRIORITY         ${doc.STM32_CAN_CAN2_IRQ_PRIORITY!"11"}
    124. 

  124. #define STM32_CAN_CAN3_IRQ_PRIORITY         ${doc.STM32_CAN_CAN3_IRQ_PRIORITY!"11"}
    125. 

  125. 

  126. /*
    127. 

  127.  * DAC driver system settings.
    128. 

  128.  */
    129. 

  129. #define STM32_DAC_DUAL_MODE                 ${doc.STM32_DAC_DUAL_MODE!"FALSE"}
    130. 

  130. #define STM32_DAC_USE_DAC1_CH1              ${doc.STM32_DAC_USE_DAC1_CH1!"FALSE"}
    131. 

  131. #define STM32_DAC_USE_DAC1_CH2              ${doc.STM32_DAC_USE_DAC1_CH2!"FALSE"}
    132. 

  132. #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     ${doc.STM32_DAC_DAC1_CH1_IRQ_PRIORITY!"10"}
    133. 

  133. #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_IRQ_PRIORITY!"10"}
    134. 

  134. #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH1_DMA_PRIORITY!"2"}
    135. 

  135. #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     ${doc.STM32_DAC_DAC1_CH2_DMA_PRIORITY!"2"}
    136. 

  136. #define STM32_DAC_DAC1_CH1_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH1_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
    137. 

  137. #define STM32_DAC_DAC1_CH2_DMA_STREAM       ${doc.STM32_DAC_DAC1_CH2_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
    138. 

  138. 

  139. /*
    140. 

  140.  * GPT driver system settings.
    141. 

  141.  */
    142. 

  142. #define STM32_GPT_USE_TIM1                  ${doc.STM32_GPT_USE_TIM1!"FALSE"}
    143. 

  143. #define STM32_GPT_USE_TIM2                  ${doc.STM32_GPT_USE_TIM2!"FALSE"}
    144. 

  144. #define STM32_GPT_USE_TIM3                  ${doc.STM32_GPT_USE_TIM3!"FALSE"}
    145. 

  145. #define STM32_GPT_USE_TIM4                  ${doc.STM32_GPT_USE_TIM4!"FALSE"}
    146. 

  146. #define STM32_GPT_USE_TIM5                  ${doc.STM32_GPT_USE_TIM5!"FALSE"}
    147. 

  147. #define STM32_GPT_USE_TIM9                  ${doc.STM32_GPT_USE_TIM9!"FALSE"}
    148. 

  148. #define STM32_GPT_USE_TIM11                 ${doc.STM32_GPT_USE_TIM11!"FALSE"}
    149. 

  149. #define STM32_GPT_TIM1_IRQ_PRIORITY         ${doc.STM32_GPT_TIM1_IRQ_PRIORITY!"7"}
    150. 

  150. #define STM32_GPT_TIM2_IRQ_PRIORITY         ${doc.STM32_GPT_TIM2_IRQ_PRIORITY!"7"}
    151. 

  151. #define STM32_GPT_TIM3_IRQ_PRIORITY         ${doc.STM32_GPT_TIM3_IRQ_PRIORITY!"7"}
    152. 

  152. #define STM32_GPT_TIM4_IRQ_PRIORITY         ${doc.STM32_GPT_TIM4_IRQ_PRIORITY!"7"}
    153. 

  153. #define STM32_GPT_TIM5_IRQ_PRIORITY         ${doc.STM32_GPT_TIM5_IRQ_PRIORITY!"7"}
    154. 

  154. #define STM32_GPT_TIM9_IRQ_PRIORITY         ${doc.STM32_GPT_TIM9_IRQ_PRIORITY!"7"}
    155. 

  155. #define STM32_GPT_TIM11_IRQ_PRIORITY        ${doc.STM32_GPT_TIM11_IRQ_PRIORITY!"7"}
    156. 

  156. 

  157. /*
    158. 

  158.  * I2C driver system settings.
    159. 

  159.  */
    160. 

  160. #define STM32_I2C_USE_I2C1                  ${doc.STM32_I2C_USE_I2C1!"FALSE"}
    161. 

  161. #define STM32_I2C_USE_I2C2                  ${doc.STM32_I2C_USE_I2C2!"FALSE"}
    162. 

  162. #define STM32_I2C_USE_I2C3                  ${doc.STM32_I2C_USE_I2C3!"FALSE"}
    163. 

  163. #define STM32_I2C_BUSY_TIMEOUT              ${doc.STM32_I2C_BUSY_TIMEOUT!"50"}
    164. 

  164. #define STM32_I2C_I2C1_RX_DMA_STREAM        ${doc.STM32_I2C_I2C1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
    165. 

  165. #define STM32_I2C_I2C1_TX_DMA_STREAM        ${doc.STM32_I2C_I2C1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
    166. 

  166. #define STM32_I2C_I2C2_RX_DMA_STREAM        ${doc.STM32_I2C_I2C2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
    167. 

  167. #define STM32_I2C_I2C2_TX_DMA_STREAM        ${doc.STM32_I2C_I2C2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
    168. 

  168. #define STM32_I2C_I2C3_RX_DMA_STREAM        ${doc.STM32_I2C_I2C3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
    169. 

  169. #define STM32_I2C_I2C3_TX_DMA_STREAM        ${doc.STM32_I2C_I2C3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
    170. 

  170. #define STM32_I2C_I2C1_IRQ_PRIORITY         ${doc.STM32_I2C_I2C1_IRQ_PRIORITY!"5"}
    171. 

  171. #define STM32_I2C_I2C2_IRQ_PRIORITY         ${doc.STM32_I2C_I2C2_IRQ_PRIORITY!"5"}
    172. 

  172. #define STM32_I2C_I2C3_IRQ_PRIORITY         ${doc.STM32_I2C_I2C3_IRQ_PRIORITY!"5"}
    173. 

  173. #define STM32_I2C_I2C1_DMA_PRIORITY         ${doc.STM32_I2C_I2C1_DMA_PRIORITY!"3"}
    174. 

  174. #define STM32_I2C_I2C2_DMA_PRIORITY         ${doc.STM32_I2C_I2C2_DMA_PRIORITY!"3"}
    175. 

  175. #define STM32_I2C_I2C3_DMA_PRIORITY         ${doc.STM32_I2C_I2C3_DMA_PRIORITY!"3"}
    176. 

  176. #define STM32_I2C_DMA_ERROR_HOOK(i2cp)      ${doc.STM32_I2C_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
    177. 

  177. 

  178. /*
    179. 

  179.  * I2S driver system settings.
    180. 

  180.  */
    181. 

  181. #define STM32_I2S_USE_SPI2                  ${doc.STM32_I2S_USE_SPI2!"FALSE"}
    182. 

  182. #define STM32_I2S_USE_SPI3                  ${doc.STM32_I2S_USE_SPI3!"FALSE"}
    183. 

  183. #define STM32_I2S_SPI2_IRQ_PRIORITY         ${doc.STM32_I2S_SPI2_IRQ_PRIORITY!"10"}
    184. 

  184. #define STM32_I2S_SPI3_IRQ_PRIORITY         ${doc.STM32_I2S_SPI3_IRQ_PRIORITY!"10"}
    185. 

  185. #define STM32_I2S_SPI2_DMA_PRIORITY         ${doc.STM32_I2S_SPI2_DMA_PRIORITY!"1"}
    186. 

  186. #define STM32_I2S_SPI3_DMA_PRIORITY         ${doc.STM32_I2S_SPI3_DMA_PRIORITY!"1"}
    187. 

  187. #define STM32_I2S_SPI2_RX_DMA_STREAM        ${doc.STM32_I2S_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
    188. 

  188. #define STM32_I2S_SPI2_TX_DMA_STREAM        ${doc.STM32_I2S_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
    189. 

  189. #define STM32_I2S_SPI3_RX_DMA_STREAM        ${doc.STM32_I2S_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
    190. 

  190. #define STM32_I2S_SPI3_TX_DMA_STREAM        ${doc.STM32_I2S_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
    191. 

  191. #define STM32_I2S_DMA_ERROR_HOOK(i2sp)      ${doc.STM32_I2S_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
    192. 

  192. 

  193. /*
    194. 

  194.  * ICU driver system settings.
    195. 

  195.  */
    196. 

  196. #define STM32_ICU_USE_TIM1                  ${doc.STM32_ICU_USE_TIM1!"FALSE"}
    197. 

  197. #define STM32_ICU_USE_TIM2                  ${doc.STM32_ICU_USE_TIM2!"FALSE"}
    198. 

  198. #define STM32_ICU_USE_TIM3                  ${doc.STM32_ICU_USE_TIM3!"FALSE"}
    199. 

  199. #define STM32_ICU_USE_TIM4                  ${doc.STM32_ICU_USE_TIM4!"FALSE"}
    200. 

  200. #define STM32_ICU_USE_TIM5                  ${doc.STM32_ICU_USE_TIM5!"FALSE"}
    201. 

  201. #define STM32_ICU_USE_TIM9                  ${doc.STM32_ICU_USE_TIM9!"FALSE"}
    202. 

  202. #define STM32_ICU_TIM1_IRQ_PRIORITY         ${doc.STM32_ICU_TIM1_IRQ_PRIORITY!"7"}
    203. 

  203. #define STM32_ICU_TIM2_IRQ_PRIORITY         ${doc.STM32_ICU_TIM2_IRQ_PRIORITY!"7"}
    204. 

  204. #define STM32_ICU_TIM3_IRQ_PRIORITY         ${doc.STM32_ICU_TIM3_IRQ_PRIORITY!"7"}
    205. 

  205. #define STM32_ICU_TIM4_IRQ_PRIORITY         ${doc.STM32_ICU_TIM4_IRQ_PRIORITY!"7"}
    206. 

  206. #define STM32_ICU_TIM5_IRQ_PRIORITY         ${doc.STM32_ICU_TIM5_IRQ_PRIORITY!"7"}
    207. 

  207. #define STM32_ICU_TIM9_IRQ_PRIORITY         ${doc.STM32_ICU_TIM9_IRQ_PRIORITY!"7"}
    208. 

  208. 

  209. /*
    210. 

  210.  * PWM driver system settings.
    211. 

  211.  */
    212. 

  212. #define STM32_PWM_USE_ADVANCED              ${doc.STM32_PWM_USE_ADVANCED!"FALSE"}
    213. 

  213. #define STM32_PWM_USE_TIM1                  ${doc.STM32_PWM_USE_TIM1!"FALSE"}
    214. 

  214. #define STM32_PWM_USE_TIM2                  ${doc.STM32_PWM_USE_TIM2!"FALSE"}
    215. 

  215. #define STM32_PWM_USE_TIM3                  ${doc.STM32_PWM_USE_TIM3!"FALSE"}
    216. 

  216. #define STM32_PWM_USE_TIM4                  ${doc.STM32_PWM_USE_TIM4!"FALSE"}
    217. 

  217. #define STM32_PWM_USE_TIM5                  ${doc.STM32_PWM_USE_TIM5!"FALSE"}
    218. 

  218. #define STM32_PWM_USE_TIM9                  ${doc.STM32_PWM_USE_TIM9!"FALSE"}
    219. 

  219. #define STM32_PWM_TIM1_IRQ_PRIORITY         ${doc.STM32_PWM_TIM1_IRQ_PRIORITY!"7"}
    220. 

  220. #define STM32_PWM_TIM2_IRQ_PRIORITY         ${doc.STM32_PWM_TIM2_IRQ_PRIORITY!"7"}
    221. 

  221. #define STM32_PWM_TIM3_IRQ_PRIORITY         ${doc.STM32_PWM_TIM3_IRQ_PRIORITY!"7"}
    222. 

  222. #define STM32_PWM_TIM4_IRQ_PRIORITY         ${doc.STM32_PWM_TIM4_IRQ_PRIORITY!"7"}
    223. 

  223. #define STM32_PWM_TIM5_IRQ_PRIORITY         ${doc.STM32_PWM_TIM5_IRQ_PRIORITY!"7"}
    224. 

  224. #define STM32_PWM_TIM9_IRQ_PRIORITY         ${doc.STM32_PWM_TIM9_IRQ_PRIORITY!"7"}
    225. 

  225. 

  226. /*
    227. 

  227.  * RTC driver system settings.
    228. 

  228.  */
    229. 

  229. #define STM32_RTC_PRESA_VALUE               ${doc.STM32_RTC_PRESA_VALUE!"32"}
    230. 

  230. #define STM32_RTC_PRESS_VALUE               ${doc.STM32_RTC_PRESS_VALUE!"1024"}
    231. 

  231. #define STM32_RTC_CR_INIT                   ${doc.STM32_RTC_CR_INIT!"0"}
    232. 

  232. #define STM32_RTC_TAMPCR_INIT               ${doc.STM32_RTC_TAMPCR_INIT!"0"}
    233. 

  233. 

  234. /*
    235. 

  235.  * SDC driver system settings.
    236. 

  236.  */
    237. 

  237. #define STM32_SDC_SDIO_DMA_PRIORITY         ${doc.STM32_SDC_SDIO_DMA_PRIORITY!"3"}
    238. 

  238. #define STM32_SDC_SDIO_IRQ_PRIORITY         ${doc.STM32_SDC_SDIO_IRQ_PRIORITY!"9"}
    239. 

  239. #define STM32_SDC_WRITE_TIMEOUT_MS          ${doc.STM32_SDC_WRITE_TIMEOUT_MS!"1000"}
    240. 

  240. #define STM32_SDC_READ_TIMEOUT_MS           ${doc.STM32_SDC_READ_TIMEOUT_MS!"1000"}
    241. 

  241. #define STM32_SDC_CLOCK_ACTIVATION_DELAY    ${doc.STM32_SDC_CLOCK_ACTIVATION_DELAY!"10"}
    242. 

  242. #define STM32_SDC_SDIO_UNALIGNED_SUPPORT    ${doc.STM32_SDC_SDIO_UNALIGNED_SUPPORT!"TRUE"}
    243. 

  243. #define STM32_SDC_SDIO_DMA_STREAM           ${doc.STM32_SDC_SDIO_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
    244. 

  244. 

  245. /*
    246. 

  246.  * SERIAL driver system settings.
    247. 

  247.  */
    248. 

  248. #define STM32_SERIAL_USE_USART1             ${doc.STM32_SERIAL_USE_USART1!"FALSE"}
    249. 

  249. #define STM32_SERIAL_USE_USART2             ${doc.STM32_SERIAL_USE_USART2!"FALSE"}
    250. 

  250. #define STM32_SERIAL_USE_USART3             ${doc.STM32_SERIAL_USE_USART3!"TRUE"}
    251. 

  251. #define STM32_SERIAL_USE_UART4              ${doc.STM32_SERIAL_USE_UART4!"FALSE"}
    252. 

  252. #define STM32_SERIAL_USE_UART5              ${doc.STM32_SERIAL_USE_UART5!"FALSE"}
    253. 

  253. #define STM32_SERIAL_USE_USART6             ${doc.STM32_SERIAL_USE_USART6!"FALSE"}
    254. 

  254. #define STM32_SERIAL_USE_UART7              ${doc.STM32_SERIAL_USE_UART7!"FALSE"}
    255. 

  255. #define STM32_SERIAL_USE_UART8              ${doc.STM32_SERIAL_USE_UART8!"FALSE"}
    256. 

  256. #define STM32_SERIAL_USART1_PRIORITY        ${doc.STM32_SERIAL_USART1_PRIORITY!"12"}
    257. 

  257. #define STM32_SERIAL_USART2_PRIORITY        ${doc.STM32_SERIAL_USART2_PRIORITY!"12"}
    258. 

  258. #define STM32_SERIAL_USART3_PRIORITY        ${doc.STM32_SERIAL_USART3_PRIORITY!"12"}
    259. 

  259. #define STM32_SERIAL_UART4_PRIORITY         ${doc.STM32_SERIAL_UART4_PRIORITY!"12"}
    260. 

  260. #define STM32_SERIAL_UART5_PRIORITY         ${doc.STM32_SERIAL_UART5_PRIORITY!"12"}
    261. 

  261. #define STM32_SERIAL_USART6_PRIORITY        ${doc.STM32_SERIAL_USART6_PRIORITY!"12"}
    262. 

  262. #define STM32_SERIAL_UART7_PRIORITY         ${doc.STM32_SERIAL_UART7_PRIORITY!"12"}
    263. 

  263. #define STM32_SERIAL_UART8_PRIORITY         ${doc.STM32_SERIAL_UART8_PRIORITY!"12"}
    264. 

  264. 

  265. /*
    266. 

  266.  * SPI driver system settings.
    267. 

  267.  */
    268. 

  268. #define STM32_SPI_USE_SPI1                  ${doc.STM32_SPI_USE_SPI1!"FALSE"}
    269. 

  269. #define STM32_SPI_USE_SPI2                  ${doc.STM32_SPI_USE_SPI2!"FALSE"}
    270. 

  270. #define STM32_SPI_USE_SPI3                  ${doc.STM32_SPI_USE_SPI3!"FALSE"}
    271. 

  271. #define STM32_SPI_USE_SPI4                  ${doc.STM32_SPI_USE_SPI4!"FALSE"}
    272. 

  272. #define STM32_SPI_USE_SPI5                  ${doc.STM32_SPI_USE_SPI5!"FALSE"}
    273. 

  273. #define STM32_SPI_SPI1_RX_DMA_STREAM        ${doc.STM32_SPI_SPI1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 0)"}
    274. 

  274. #define STM32_SPI_SPI1_TX_DMA_STREAM        ${doc.STM32_SPI_SPI1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 3)"}
    275. 

  275. #define STM32_SPI_SPI2_RX_DMA_STREAM        ${doc.STM32_SPI_SPI2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
    276. 

  276. #define STM32_SPI_SPI2_TX_DMA_STREAM        ${doc.STM32_SPI_SPI2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
    277. 

  277. #define STM32_SPI_SPI3_RX_DMA_STREAM        ${doc.STM32_SPI_SPI3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
    278. 

  278. #define STM32_SPI_SPI3_TX_DMA_STREAM        ${doc.STM32_SPI_SPI3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
    279. 

  279. #define STM32_SPI_SPI4_RX_DMA_STREAM        ${doc.STM32_SPI_SPI4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 4)"}
    280. 

  280. #define STM32_SPI_SPI4_TX_DMA_STREAM        ${doc.STM32_SPI_SPI4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 1)"}
    281. 

  281. #define STM32_SPI_SPI5_RX_DMA_STREAM        ${doc.STM32_SPI_SPI5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
    282. 

  282. #define STM32_SPI_SPI5_TX_DMA_STREAM        ${doc.STM32_SPI_SPI5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 6)"}
    283. 

  283. #define STM32_SPI_SPI1_DMA_PRIORITY         ${doc.STM32_SPI_SPI1_DMA_PRIORITY!"1"}
    284. 

  284. #define STM32_SPI_SPI2_DMA_PRIORITY         ${doc.STM32_SPI_SPI2_DMA_PRIORITY!"1"}
    285. 

  285. #define STM32_SPI_SPI3_DMA_PRIORITY         ${doc.STM32_SPI_SPI3_DMA_PRIORITY!"1"}
    286. 

  286. #define STM32_SPI_SPI4_DMA_PRIORITY         ${doc.STM32_SPI_SPI4_DMA_PRIORITY!"1"}
    287. 

  287. #define STM32_SPI_SPI5_DMA_PRIORITY         ${doc.STM32_SPI_SPI5_DMA_PRIORITY!"1"}
    288. 

  288. #define STM32_SPI_SPI1_IRQ_PRIORITY         ${doc.STM32_SPI_SPI1_IRQ_PRIORITY!"10"}
    289. 

  289. #define STM32_SPI_SPI2_IRQ_PRIORITY         ${doc.STM32_SPI_SPI2_IRQ_PRIORITY!"10"}
    290. 

  290. #define STM32_SPI_SPI3_IRQ_PRIORITY         ${doc.STM32_SPI_SPI3_IRQ_PRIORITY!"10"}
    291. 

  291. #define STM32_SPI_SPI4_IRQ_PRIORITY         ${doc.STM32_SPI_SPI4_IRQ_PRIORITY!"10"}
    292. 

  292. #define STM32_SPI_SPI5_IRQ_PRIORITY         ${doc.STM32_SPI_SPI5_IRQ_PRIORITY!"10"}
    293. 

  293. #define STM32_SPI_DMA_ERROR_HOOK(spip)      ${doc.STM32_SPI_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
    294. 

  294. 

  295. /*
    296. 

  296.  * ST driver system settings.
    297. 

  297.  */
    298. 

  298. #define STM32_ST_IRQ_PRIORITY               ${doc.STM32_ST_IRQ_PRIORITY!"8"}
    299. 

  299. #define STM32_ST_USE_TIMER                  ${doc.STM32_ST_USE_TIMER!"2"}
    300. 

  300. 

  301. /*
    302. 

  302.  * UART driver system settings.
    303. 

  303.  */
    304. 

  304. #define STM32_UART_USE_USART1               ${doc.STM32_UART_USE_USART1!"FALSE"}
    305. 

  305. #define STM32_UART_USE_USART2               ${doc.STM32_UART_USE_USART2!"FALSE"}
    306. 

  306. #define STM32_UART_USE_USART3               ${doc.STM32_UART_USE_USART3!"FALSE"}
    307. 

  307. #define STM32_UART_USE_UART4                ${doc.STM32_UART_USE_UART4!"FALSE"}
    308. 

  308. #define STM32_UART_USE_UART5                ${doc.STM32_UART_USE_UART5!"FALSE"}
    309. 

  309. #define STM32_UART_USE_USART6               ${doc.STM32_UART_USE_USART6!"FALSE"}
    310. 

  310. #define STM32_UART_USE_UART7                ${doc.STM32_UART_USE_UART7!"FALSE"}
    311. 

  311. #define STM32_UART_USE_UART8                ${doc.STM32_UART_USE_UART8!"FALSE"}
    312. 

  312. #define STM32_UART_USART1_RX_DMA_STREAM     ${doc.STM32_UART_USART1_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 5)"}
    313. 

  313. #define STM32_UART_USART1_TX_DMA_STREAM     ${doc.STM32_UART_USART1_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
    314. 

  314. #define STM32_UART_USART2_RX_DMA_STREAM     ${doc.STM32_UART_USART2_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 5)"}
    315. 

  315. #define STM32_UART_USART2_TX_DMA_STREAM     ${doc.STM32_UART_USART2_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
    316. 

  316. #define STM32_UART_USART3_RX_DMA_STREAM     ${doc.STM32_UART_USART3_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
    317. 

  317. #define STM32_UART_USART3_TX_DMA_STREAM     ${doc.STM32_UART_USART3_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
    318. 

  318. #define STM32_UART_UART4_RX_DMA_STREAM      ${doc.STM32_UART_UART4_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 2)"}
    319. 

  319. #define STM32_UART_UART4_TX_DMA_STREAM      ${doc.STM32_UART_UART4_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 4)"}
    320. 

  320. #define STM32_UART_UART5_RX_DMA_STREAM      ${doc.STM32_UART_UART5_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
    321. 

  321. #define STM32_UART_UART5_TX_DMA_STREAM      ${doc.STM32_UART_UART5_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 7)"}
    322. 

  322. #define STM32_UART_USART6_RX_DMA_STREAM     ${doc.STM32_UART_USART6_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 2)"}
    323. 

  323. #define STM32_UART_USART6_TX_DMA_STREAM     ${doc.STM32_UART_USART6_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(2, 7)"}
    324. 

  324. #define STM32_UART_UART7_RX_DMA_STREAM      ${doc.STM32_UART_UART7_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 3)"}
    325. 

  325. #define STM32_UART_UART7_TX_DMA_STREAM      ${doc.STM32_UART_UART7_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 1)"}
    326. 

  326. #define STM32_UART_UART8_RX_DMA_STREAM      ${doc.STM32_UART_UART8_RX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 6)"}
    327. 

  327. #define STM32_UART_UART8_TX_DMA_STREAM      ${doc.STM32_UART_UART8_TX_DMA_STREAM!"STM32_DMA_STREAM_ID(1, 0)"}
    328. 

  328. #define STM32_UART_USART1_IRQ_PRIORITY      ${doc.STM32_UART_USART1_IRQ_PRIORITY!"12"}
    329. 

  329. #define STM32_UART_USART2_IRQ_PRIORITY      ${doc.STM32_UART_USART2_IRQ_PRIORITY!"12"}
    330. 

  330. #define STM32_UART_USART3_IRQ_PRIORITY      ${doc.STM32_UART_USART3_IRQ_PRIORITY!"12"}
    331. 

  331. #define STM32_UART_UART4_IRQ_PRIORITY       ${doc.STM32_UART_UART4_IRQ_PRIORITY!"12"}
    332. 

  332. #define STM32_UART_UART5_IRQ_PRIORITY       ${doc.STM32_UART_UART5_IRQ_PRIORITY!"12"}
    333. 

  333. #define STM32_UART_USART6_IRQ_PRIORITY      ${doc.STM32_UART_USART6_IRQ_PRIORITY!"12"}
    334. 

  334. #define STM32_UART_UART7_IRQ_PRIORITY       ${doc.STM32_UART_UART7_IRQ_PRIORITY!"12"}
    335. 

  335. #define STM32_UART_UART8_IRQ_PRIORITY       ${doc.STM32_UART_UART8_IRQ_PRIORITY!"12"}
    336. 

  336. #define STM32_UART_USART1_DMA_PRIORITY      ${doc.STM32_UART_USART1_DMA_PRIORITY!"0"}
    337. 

  337. #define STM32_UART_USART2_DMA_PRIORITY      ${doc.STM32_UART_USART2_DMA_PRIORITY!"0"}
    338. 

  338. #define STM32_UART_USART3_DMA_PRIORITY      ${doc.STM32_UART_USART3_DMA_PRIORITY!"0"}
    339. 

  339. #define STM32_UART_UART4_DMA_PRIORITY       ${doc.STM32_UART_UART4_DMA_PRIORITY!"0"}
    340. 

  340. #define STM32_UART_UART5_DMA_PRIORITY       ${doc.STM32_UART_UART5_DMA_PRIORITY!"0"}
    341. 

  341. #define STM32_UART_USART6_DMA_PRIORITY      ${doc.STM32_UART_USART6_DMA_PRIORITY!"0"}
    342. 

  342. #define STM32_UART_UART7_DMA_PRIORITY       ${doc.STM32_UART_UART7_DMA_PRIORITY!"0"}
    343. 

  343. #define STM32_UART_UART8_DMA_PRIORITY       ${doc.STM32_UART_UART8_DMA_PRIORITY!"0"}
    344. 

  344. #define STM32_UART_DMA_ERROR_HOOK(uartp)    ${doc.STM32_UART_DMA_ERROR_HOOK!"osalSysHalt(\"DMA failure\")"}
    345. 

  345. 

  346. /*
    347. 

  347.  * USB driver system settings.
    348. 

  348.  */
    349. 

  349. #define STM32_USB_USE_OTG1                  ${doc.STM32_USB_USE_OTG1!"FALSE"}
    350. 

  350. #define STM32_USB_OTG1_IRQ_PRIORITY         ${doc.STM32_USB_OTG1_IRQ_PRIORITY!"14"}
    351. 

  351. #define STM32_USB_OTG1_RX_FIFO_SIZE         ${doc.STM32_USB_OTG1_RX_FIFO_SIZE!"512"}
    352. 

  352. #define STM32_USB_HOST_WAKEUP_DURATION      ${doc.STM32_USB_HOST_WAKEUP_DURATION!"2"}
    353. 

  353. 

  354. /*
    355. 

  355.  * WDG driver system settings.
    356. 

  356.  */
    357. 

  357. #define STM32_WDG_USE_IWDG                  ${doc.STM32_WDG_USE_IWDG!"FALSE"}
    358. 

  358. 

  359. #endif /* MCUCONF_H */
    360.