mcuconf.h 14 KB

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  1. /*
  2. ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
  3. Licensed under the Apache License, Version 2.0 (the "License");
  4. you may not use this file except in compliance with the License.
  5. You may obtain a copy of the License at
  6. http://www.apache.org/licenses/LICENSE-2.0
  7. Unless required by applicable law or agreed to in writing, software
  8. distributed under the License is distributed on an "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  10. See the License for the specific language governing permissions and
  11. limitations under the License.
  12. */
  13. #ifndef MCUCONF_H
  14. #define MCUCONF_H
  15. /*
  16. * STM32F4xx drivers configuration.
  17. * The following settings override the default settings present in
  18. * the various device driver implementation headers.
  19. * Note that the settings for each driver only have effect if the whole
  20. * driver is enabled in halconf.h.
  21. *
  22. * IRQ priorities:
  23. * 15...0 Lowest...Highest.
  24. *
  25. * DMA priorities:
  26. * 0...3 Lowest...Highest.
  27. */
  28. #define STM32F4xx_MCUCONF
  29. #define STM32F405_MCUCONF
  30. #define STM32F415_MCUCONF
  31. #define STM32F407_MCUCONF
  32. #define STM32F417_MCUCONF
  33. /*
  34. * HAL driver system settings.
  35. */
  36. #define STM32_NO_INIT FALSE
  37. #define STM32_PVD_ENABLE FALSE
  38. #define STM32_PLS STM32_PLS_LEV0
  39. #define STM32_BKPRAM_ENABLE FALSE
  40. #define STM32_HSI_ENABLED TRUE
  41. #define STM32_LSI_ENABLED TRUE
  42. #define STM32_HSE_ENABLED TRUE
  43. #define STM32_LSE_ENABLED FALSE
  44. #define STM32_CLOCK48_REQUIRED TRUE
  45. #define STM32_SW STM32_SW_PLL
  46. #define STM32_PLLSRC STM32_PLLSRC_HSE
  47. #define STM32_PLLM_VALUE 8
  48. #define STM32_PLLN_VALUE 336
  49. #define STM32_PLLP_VALUE 2
  50. #define STM32_PLLQ_VALUE 7
  51. #define STM32_HPRE STM32_HPRE_DIV1
  52. #define STM32_PPRE1 STM32_PPRE1_DIV4
  53. #define STM32_PPRE2 STM32_PPRE2_DIV2
  54. #define STM32_RTCSEL STM32_RTCSEL_LSI
  55. #define STM32_RTCPRE_VALUE 8
  56. #define STM32_MCO1SEL STM32_MCO1SEL_HSI
  57. #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
  58. #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
  59. #define STM32_MCO2PRE STM32_MCO2PRE_DIV5
  60. #define STM32_I2SSRC STM32_I2SSRC_CKIN
  61. #define STM32_PLLI2SN_VALUE 192
  62. #define STM32_PLLI2SR_VALUE 5
  63. /*
  64. * IRQ system settings.
  65. */
  66. #define STM32_IRQ_EXTI0_PRIORITY 6
  67. #define STM32_IRQ_EXTI1_PRIORITY 6
  68. #define STM32_IRQ_EXTI2_PRIORITY 6
  69. #define STM32_IRQ_EXTI3_PRIORITY 6
  70. #define STM32_IRQ_EXTI4_PRIORITY 6
  71. #define STM32_IRQ_EXTI5_9_PRIORITY 6
  72. #define STM32_IRQ_EXTI10_15_PRIORITY 6
  73. #define STM32_IRQ_EXTI16_PRIORITY 6
  74. #define STM32_IRQ_EXTI17_PRIORITY 15
  75. #define STM32_IRQ_EXTI18_PRIORITY 6
  76. #define STM32_IRQ_EXTI19_PRIORITY 6
  77. #define STM32_IRQ_EXTI20_PRIORITY 6
  78. #define STM32_IRQ_EXTI21_PRIORITY 15
  79. #define STM32_IRQ_EXTI22_PRIORITY 15
  80. /*
  81. * ADC driver system settings.
  82. */
  83. #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
  84. #define STM32_ADC_USE_ADC1 FALSE
  85. #define STM32_ADC_USE_ADC2 FALSE
  86. #define STM32_ADC_USE_ADC3 FALSE
  87. #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
  88. #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
  89. #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
  90. #define STM32_ADC_ADC1_DMA_PRIORITY 2
  91. #define STM32_ADC_ADC2_DMA_PRIORITY 2
  92. #define STM32_ADC_ADC3_DMA_PRIORITY 2
  93. #define STM32_ADC_IRQ_PRIORITY 6
  94. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
  95. #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
  96. #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
  97. /*
  98. * CAN driver system settings.
  99. */
  100. #define STM32_CAN_USE_CAN1 FALSE
  101. #define STM32_CAN_USE_CAN2 FALSE
  102. #define STM32_CAN_CAN1_IRQ_PRIORITY 11
  103. #define STM32_CAN_CAN2_IRQ_PRIORITY 11
  104. /*
  105. * DAC driver system settings.
  106. */
  107. #define STM32_DAC_DUAL_MODE FALSE
  108. #define STM32_DAC_USE_DAC1_CH1 FALSE
  109. #define STM32_DAC_USE_DAC1_CH2 FALSE
  110. #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
  111. #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
  112. #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
  113. #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
  114. #define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  115. #define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  116. /*
  117. * GPT driver system settings.
  118. */
  119. #define STM32_GPT_USE_TIM1 FALSE
  120. #define STM32_GPT_USE_TIM2 FALSE
  121. #define STM32_GPT_USE_TIM3 FALSE
  122. #define STM32_GPT_USE_TIM4 FALSE
  123. #define STM32_GPT_USE_TIM5 FALSE
  124. #define STM32_GPT_USE_TIM6 FALSE
  125. #define STM32_GPT_USE_TIM7 FALSE
  126. #define STM32_GPT_USE_TIM8 FALSE
  127. #define STM32_GPT_USE_TIM9 FALSE
  128. #define STM32_GPT_USE_TIM11 FALSE
  129. #define STM32_GPT_USE_TIM12 FALSE
  130. #define STM32_GPT_USE_TIM14 FALSE
  131. #define STM32_GPT_TIM1_IRQ_PRIORITY 7
  132. #define STM32_GPT_TIM2_IRQ_PRIORITY 7
  133. #define STM32_GPT_TIM3_IRQ_PRIORITY 7
  134. #define STM32_GPT_TIM4_IRQ_PRIORITY 7
  135. #define STM32_GPT_TIM5_IRQ_PRIORITY 7
  136. #define STM32_GPT_TIM6_IRQ_PRIORITY 7
  137. #define STM32_GPT_TIM7_IRQ_PRIORITY 7
  138. #define STM32_GPT_TIM8_IRQ_PRIORITY 7
  139. #define STM32_GPT_TIM9_IRQ_PRIORITY 7
  140. #define STM32_GPT_TIM11_IRQ_PRIORITY 7
  141. #define STM32_GPT_TIM12_IRQ_PRIORITY 7
  142. #define STM32_GPT_TIM14_IRQ_PRIORITY 7
  143. /*
  144. * I2C driver system settings.
  145. */
  146. #define STM32_I2C_USE_I2C1 FALSE
  147. #define STM32_I2C_USE_I2C2 FALSE
  148. #define STM32_I2C_USE_I2C3 FALSE
  149. #define STM32_I2C_BUSY_TIMEOUT 50
  150. #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  151. #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  152. #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  153. #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  154. #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  155. #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  156. #define STM32_I2C_I2C1_IRQ_PRIORITY 5
  157. #define STM32_I2C_I2C2_IRQ_PRIORITY 5
  158. #define STM32_I2C_I2C3_IRQ_PRIORITY 5
  159. #define STM32_I2C_I2C1_DMA_PRIORITY 3
  160. #define STM32_I2C_I2C2_DMA_PRIORITY 3
  161. #define STM32_I2C_I2C3_DMA_PRIORITY 3
  162. #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
  163. /*
  164. * I2S driver system settings.
  165. */
  166. #define STM32_I2S_USE_SPI2 FALSE
  167. #define STM32_I2S_USE_SPI3 FALSE
  168. #define STM32_I2S_SPI2_IRQ_PRIORITY 10
  169. #define STM32_I2S_SPI3_IRQ_PRIORITY 10
  170. #define STM32_I2S_SPI2_DMA_PRIORITY 1
  171. #define STM32_I2S_SPI3_DMA_PRIORITY 1
  172. #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  173. #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  174. #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  175. #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  176. #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
  177. /*
  178. * ICU driver system settings.
  179. */
  180. #define STM32_ICU_USE_TIM1 FALSE
  181. #define STM32_ICU_USE_TIM2 FALSE
  182. #define STM32_ICU_USE_TIM3 FALSE
  183. #define STM32_ICU_USE_TIM4 FALSE
  184. #define STM32_ICU_USE_TIM5 FALSE
  185. #define STM32_ICU_USE_TIM8 FALSE
  186. #define STM32_ICU_USE_TIM9 FALSE
  187. #define STM32_ICU_TIM1_IRQ_PRIORITY 7
  188. #define STM32_ICU_TIM2_IRQ_PRIORITY 7
  189. #define STM32_ICU_TIM3_IRQ_PRIORITY 7
  190. #define STM32_ICU_TIM4_IRQ_PRIORITY 7
  191. #define STM32_ICU_TIM5_IRQ_PRIORITY 7
  192. #define STM32_ICU_TIM8_IRQ_PRIORITY 7
  193. #define STM32_ICU_TIM9_IRQ_PRIORITY 7
  194. /*
  195. * MAC driver system settings.
  196. */
  197. #define STM32_MAC_TRANSMIT_BUFFERS 2
  198. #define STM32_MAC_RECEIVE_BUFFERS 4
  199. #define STM32_MAC_BUFFERS_SIZE 1522
  200. #define STM32_MAC_PHY_TIMEOUT 100
  201. #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
  202. #define STM32_MAC_ETH1_IRQ_PRIORITY 13
  203. #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
  204. /*
  205. * PWM driver system settings.
  206. */
  207. #define STM32_PWM_USE_ADVANCED FALSE
  208. #define STM32_PWM_USE_TIM1 FALSE
  209. #define STM32_PWM_USE_TIM2 FALSE
  210. #define STM32_PWM_USE_TIM3 FALSE
  211. #define STM32_PWM_USE_TIM4 FALSE
  212. #define STM32_PWM_USE_TIM5 FALSE
  213. #define STM32_PWM_USE_TIM8 FALSE
  214. #define STM32_PWM_USE_TIM9 FALSE
  215. #define STM32_PWM_TIM1_IRQ_PRIORITY 7
  216. #define STM32_PWM_TIM2_IRQ_PRIORITY 7
  217. #define STM32_PWM_TIM3_IRQ_PRIORITY 7
  218. #define STM32_PWM_TIM4_IRQ_PRIORITY 7
  219. #define STM32_PWM_TIM5_IRQ_PRIORITY 7
  220. #define STM32_PWM_TIM8_IRQ_PRIORITY 7
  221. #define STM32_PWM_TIM9_IRQ_PRIORITY 7
  222. /*
  223. * RTC driver system settings.
  224. */
  225. #define STM32_RTC_PRESA_VALUE 32
  226. #define STM32_RTC_PRESS_VALUE 1024
  227. #define STM32_RTC_CR_INIT 0
  228. #define STM32_RTC_TAMPCR_INIT 0
  229. /*
  230. * SDC driver system settings.
  231. */
  232. #define STM32_SDC_SDIO_DMA_PRIORITY 3
  233. #define STM32_SDC_SDIO_IRQ_PRIORITY 9
  234. #define STM32_SDC_WRITE_TIMEOUT_MS 1000
  235. #define STM32_SDC_READ_TIMEOUT_MS 1000
  236. #define STM32_SDC_CLOCK_ACTIVATION_DELAY 10
  237. #define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE
  238. #define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
  239. /*
  240. * SERIAL driver system settings.
  241. */
  242. #define STM32_SERIAL_USE_USART1 FALSE
  243. #define STM32_SERIAL_USE_USART2 TRUE
  244. #define STM32_SERIAL_USE_USART3 FALSE
  245. #define STM32_SERIAL_USE_UART4 FALSE
  246. #define STM32_SERIAL_USE_UART5 FALSE
  247. #define STM32_SERIAL_USE_USART6 FALSE
  248. #define STM32_SERIAL_USART1_PRIORITY 12
  249. #define STM32_SERIAL_USART2_PRIORITY 12
  250. #define STM32_SERIAL_USART3_PRIORITY 12
  251. #define STM32_SERIAL_UART4_PRIORITY 12
  252. #define STM32_SERIAL_UART5_PRIORITY 12
  253. #define STM32_SERIAL_USART6_PRIORITY 12
  254. /*
  255. * SPI driver system settings.
  256. */
  257. #define STM32_SPI_USE_SPI1 TRUE
  258. #define STM32_SPI_USE_SPI2 FALSE
  259. #define STM32_SPI_USE_SPI3 FALSE
  260. #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
  261. #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
  262. #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  263. #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  264. #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  265. #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  266. #define STM32_SPI_SPI1_DMA_PRIORITY 1
  267. #define STM32_SPI_SPI2_DMA_PRIORITY 1
  268. #define STM32_SPI_SPI3_DMA_PRIORITY 1
  269. #define STM32_SPI_SPI1_IRQ_PRIORITY 10
  270. #define STM32_SPI_SPI2_IRQ_PRIORITY 10
  271. #define STM32_SPI_SPI3_IRQ_PRIORITY 10
  272. #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
  273. /*
  274. * ST driver system settings.
  275. */
  276. #define STM32_ST_IRQ_PRIORITY 8
  277. #define STM32_ST_USE_TIMER 2
  278. /*
  279. * UART driver system settings.
  280. */
  281. #define STM32_UART_USE_USART1 FALSE
  282. #define STM32_UART_USE_USART2 FALSE
  283. #define STM32_UART_USE_USART3 FALSE
  284. #define STM32_UART_USE_UART4 FALSE
  285. #define STM32_UART_USE_UART5 FALSE
  286. #define STM32_UART_USE_USART6 FALSE
  287. #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
  288. #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
  289. #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  290. #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  291. #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
  292. #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  293. #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  294. #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  295. #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  296. #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  297. #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
  298. #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
  299. #define STM32_UART_USART1_IRQ_PRIORITY 12
  300. #define STM32_UART_USART2_IRQ_PRIORITY 12
  301. #define STM32_UART_USART3_IRQ_PRIORITY 12
  302. #define STM32_UART_UART4_IRQ_PRIORITY 12
  303. #define STM32_UART_UART5_IRQ_PRIORITY 12
  304. #define STM32_UART_USART6_IRQ_PRIORITY 12
  305. #define STM32_UART_USART1_DMA_PRIORITY 0
  306. #define STM32_UART_USART2_DMA_PRIORITY 0
  307. #define STM32_UART_USART3_DMA_PRIORITY 0
  308. #define STM32_UART_UART4_DMA_PRIORITY 0
  309. #define STM32_UART_UART5_DMA_PRIORITY 0
  310. #define STM32_UART_USART6_DMA_PRIORITY 0
  311. #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
  312. /*
  313. * USB driver system settings.
  314. */
  315. #define STM32_USB_USE_OTG1 TRUE
  316. #define STM32_USB_USE_OTG2 FALSE
  317. #define STM32_USB_OTG1_IRQ_PRIORITY 14
  318. #define STM32_USB_OTG2_IRQ_PRIORITY 14
  319. #define STM32_USB_OTG1_RX_FIFO_SIZE 512
  320. #define STM32_USB_OTG2_RX_FIFO_SIZE 1024
  321. #define STM32_USB_HOST_WAKEUP_DURATION 2
  322. /*
  323. * WDG driver system settings.
  324. */
  325. #define STM32_WDG_USE_IWDG FALSE
  326. #endif /* MCUCONF_H */