mcuconf.h 9.9 KB

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  1. /*
  2. ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
  3. Licensed under the Apache License, Version 2.0 (the "License");
  4. you may not use this file except in compliance with the License.
  5. You may obtain a copy of the License at
  6. http://www.apache.org/licenses/LICENSE-2.0
  7. Unless required by applicable law or agreed to in writing, software
  8. distributed under the License is distributed on an "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  10. See the License for the specific language governing permissions and
  11. limitations under the License.
  12. */
  13. #ifndef MCUCONF_H
  14. #define MCUCONF_H
  15. /*
  16. * STM32F4xx drivers configuration.
  17. * The following settings override the default settings present in
  18. * the various device driver implementation headers.
  19. * Note that the settings for each driver only have effect if the whole
  20. * driver is enabled in halconf.h.
  21. *
  22. * IRQ priorities:
  23. * 15...0 Lowest...Highest.
  24. *
  25. * DMA priorities:
  26. * 0...3 Lowest...Highest.
  27. */
  28. #define STM32F4xx_MCUCONF
  29. /*
  30. * HAL driver system settings.
  31. */
  32. #define STM32_NO_INIT FALSE
  33. #define STM32_HSI_ENABLED TRUE
  34. #define STM32_LSI_ENABLED TRUE
  35. #define STM32_HSE_ENABLED TRUE
  36. #define STM32_LSE_ENABLED FALSE
  37. #define STM32_CLOCK48_REQUIRED TRUE
  38. #define STM32_SW STM32_SW_PLL
  39. #define STM32_PLLSRC STM32_PLLSRC_HSE
  40. #define STM32_PLLM_VALUE 8
  41. #define STM32_PLLN_VALUE 336
  42. #define STM32_PLLP_VALUE 4
  43. #define STM32_PLLQ_VALUE 7
  44. #define STM32_HPRE STM32_HPRE_DIV1
  45. #define STM32_PPRE1 STM32_PPRE1_DIV2
  46. #define STM32_PPRE2 STM32_PPRE2_DIV1
  47. #define STM32_RTCSEL STM32_RTCSEL_LSI
  48. #define STM32_RTCPRE_VALUE 8
  49. #define STM32_MCO1SEL STM32_MCO1SEL_HSI
  50. #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
  51. #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
  52. #define STM32_MCO2PRE STM32_MCO2PRE_DIV5
  53. #define STM32_I2SSRC STM32_I2SSRC_CKIN
  54. #define STM32_PLLI2SN_VALUE 192
  55. #define STM32_PLLI2SR_VALUE 5
  56. #define STM32_PVD_ENABLE FALSE
  57. #define STM32_PLS STM32_PLS_LEV0
  58. #define STM32_BKPRAM_ENABLE FALSE
  59. /*
  60. * IRQ system settings.
  61. */
  62. #define STM32_IRQ_EXTI0_PRIORITY 6
  63. #define STM32_IRQ_EXTI1_PRIORITY 6
  64. #define STM32_IRQ_EXTI2_PRIORITY 6
  65. #define STM32_IRQ_EXTI3_PRIORITY 6
  66. #define STM32_IRQ_EXTI4_PRIORITY 6
  67. #define STM32_IRQ_EXTI5_9_PRIORITY 6
  68. #define STM32_IRQ_EXTI10_15_PRIORITY 6
  69. #define STM32_IRQ_EXTI16_PRIORITY 6
  70. #define STM32_IRQ_EXTI17_PRIORITY 15
  71. #define STM32_IRQ_EXTI18_PRIORITY 6
  72. #define STM32_IRQ_EXTI19_PRIORITY 6
  73. #define STM32_IRQ_EXTI20_PRIORITY 6
  74. #define STM32_IRQ_EXTI21_PRIORITY 15
  75. #define STM32_IRQ_EXTI22_PRIORITY 15
  76. /*
  77. * ADC driver system settings.
  78. */
  79. #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
  80. #define STM32_ADC_USE_ADC1 FALSE
  81. #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
  82. #define STM32_ADC_ADC1_DMA_PRIORITY 2
  83. #define STM32_ADC_IRQ_PRIORITY 6
  84. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
  85. /*
  86. * GPT driver system settings.
  87. */
  88. #define STM32_GPT_USE_TIM1 FALSE
  89. #define STM32_GPT_USE_TIM2 FALSE
  90. #define STM32_GPT_USE_TIM3 FALSE
  91. #define STM32_GPT_USE_TIM4 FALSE
  92. #define STM32_GPT_USE_TIM5 FALSE
  93. #define STM32_GPT_USE_TIM9 FALSE
  94. #define STM32_GPT_USE_TIM11 FALSE
  95. #define STM32_GPT_TIM1_IRQ_PRIORITY 7
  96. #define STM32_GPT_TIM2_IRQ_PRIORITY 7
  97. #define STM32_GPT_TIM3_IRQ_PRIORITY 7
  98. #define STM32_GPT_TIM4_IRQ_PRIORITY 7
  99. #define STM32_GPT_TIM5_IRQ_PRIORITY 7
  100. #define STM32_GPT_TIM9_IRQ_PRIORITY 7
  101. #define STM32_GPT_TIM11_IRQ_PRIORITY 7
  102. /*
  103. * I2C driver system settings.
  104. */
  105. #define STM32_I2C_USE_I2C1 TRUE
  106. #define STM32_I2C_USE_I2C2 FALSE
  107. #define STM32_I2C_USE_I2C3 FALSE
  108. #define STM32_I2C_BUSY_TIMEOUT 50
  109. #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  110. #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  111. #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  112. #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  113. #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  114. #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  115. #define STM32_I2C_I2C1_IRQ_PRIORITY 5
  116. #define STM32_I2C_I2C2_IRQ_PRIORITY 5
  117. #define STM32_I2C_I2C3_IRQ_PRIORITY 5
  118. #define STM32_I2C_I2C1_DMA_PRIORITY 3
  119. #define STM32_I2C_I2C2_DMA_PRIORITY 3
  120. #define STM32_I2C_I2C3_DMA_PRIORITY 3
  121. #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
  122. /*
  123. * I2S driver system settings.
  124. */
  125. #define STM32_I2S_USE_SPI2 FALSE
  126. #define STM32_I2S_USE_SPI3 FALSE
  127. #define STM32_I2S_SPI2_IRQ_PRIORITY 10
  128. #define STM32_I2S_SPI3_IRQ_PRIORITY 10
  129. #define STM32_I2S_SPI2_DMA_PRIORITY 1
  130. #define STM32_I2S_SPI3_DMA_PRIORITY 1
  131. #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  132. #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  133. #define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  134. #define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  135. #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
  136. /*
  137. * ICU driver system settings.
  138. */
  139. #define STM32_ICU_USE_TIM1 FALSE
  140. #define STM32_ICU_USE_TIM2 FALSE
  141. #define STM32_ICU_USE_TIM3 FALSE
  142. #define STM32_ICU_USE_TIM4 FALSE
  143. #define STM32_ICU_USE_TIM5 FALSE
  144. #define STM32_ICU_USE_TIM9 FALSE
  145. #define STM32_ICU_TIM1_IRQ_PRIORITY 7
  146. #define STM32_ICU_TIM2_IRQ_PRIORITY 7
  147. #define STM32_ICU_TIM3_IRQ_PRIORITY 7
  148. #define STM32_ICU_TIM4_IRQ_PRIORITY 7
  149. #define STM32_ICU_TIM5_IRQ_PRIORITY 7
  150. #define STM32_ICU_TIM9_IRQ_PRIORITY 7
  151. /*
  152. * PWM driver system settings.
  153. */
  154. #define STM32_PWM_USE_ADVANCED FALSE
  155. #define STM32_PWM_USE_TIM1 FALSE
  156. #define STM32_PWM_USE_TIM2 FALSE
  157. #define STM32_PWM_USE_TIM3 FALSE
  158. #define STM32_PWM_USE_TIM4 FALSE
  159. #define STM32_PWM_USE_TIM5 FALSE
  160. #define STM32_PWM_USE_TIM9 FALSE
  161. #define STM32_PWM_TIM1_IRQ_PRIORITY 7
  162. #define STM32_PWM_TIM2_IRQ_PRIORITY 7
  163. #define STM32_PWM_TIM3_IRQ_PRIORITY 7
  164. #define STM32_PWM_TIM4_IRQ_PRIORITY 7
  165. #define STM32_PWM_TIM5_IRQ_PRIORITY 7
  166. #define STM32_PWM_TIM9_IRQ_PRIORITY 7
  167. /*
  168. * SERIAL driver system settings.
  169. */
  170. #define STM32_SERIAL_USE_USART1 FALSE
  171. #define STM32_SERIAL_USE_USART2 TRUE
  172. #define STM32_SERIAL_USE_USART6 FALSE
  173. #define STM32_SERIAL_USART1_PRIORITY 12
  174. #define STM32_SERIAL_USART2_PRIORITY 12
  175. #define STM32_SERIAL_USART6_PRIORITY 12
  176. /*
  177. * SPI driver system settings.
  178. */
  179. #define STM32_SPI_USE_SPI1 FALSE
  180. #define STM32_SPI_USE_SPI2 FALSE
  181. #define STM32_SPI_USE_SPI3 FALSE
  182. #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
  183. #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
  184. #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  185. #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  186. #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
  187. #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
  188. #define STM32_SPI_SPI1_DMA_PRIORITY 1
  189. #define STM32_SPI_SPI2_DMA_PRIORITY 1
  190. #define STM32_SPI_SPI3_DMA_PRIORITY 1
  191. #define STM32_SPI_SPI1_IRQ_PRIORITY 10
  192. #define STM32_SPI_SPI2_IRQ_PRIORITY 10
  193. #define STM32_SPI_SPI3_IRQ_PRIORITY 10
  194. #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
  195. /*
  196. * ST driver system settings.
  197. */
  198. #define STM32_ST_IRQ_PRIORITY 8
  199. #define STM32_ST_USE_TIMER 2
  200. /*
  201. * UART driver system settings.
  202. */
  203. #define STM32_UART_USE_USART1 FALSE
  204. #define STM32_UART_USE_USART2 FALSE
  205. #define STM32_UART_USE_USART6 FALSE
  206. #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
  207. #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
  208. #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  209. #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
  210. #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
  211. #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
  212. #define STM32_UART_USART1_IRQ_PRIORITY 12
  213. #define STM32_UART_USART2_IRQ_PRIORITY 12
  214. #define STM32_UART_USART6_IRQ_PRIORITY 12
  215. #define STM32_UART_USART1_DMA_PRIORITY 0
  216. #define STM32_UART_USART2_DMA_PRIORITY 0
  217. #define STM32_UART_USART6_DMA_PRIORITY 0
  218. #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
  219. /*
  220. * USB driver system settings.
  221. */
  222. #define STM32_USB_USE_OTG1 TRUE
  223. #define STM32_USB_OTG1_IRQ_PRIORITY 14
  224. #define STM32_USB_OTG1_RX_FIFO_SIZE 512
  225. #define STM32_USB_OTG_THREAD_PRIO LOWPRIO
  226. #define STM32_USB_OTG_THREAD_STACK_SIZE 128
  227. #define STM32_USB_OTGFIFO_FILL_BASEPRI 0
  228. /*
  229. * WDG driver system settings.
  230. */
  231. #define STM32_WDG_USE_IWDG FALSE
  232. #endif /* MCUCONF_H */