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mcuconf.h.ftl

mcuconf.h.ftl 14 KB
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  1. [#ftl]
    2. 

  2. [@pp.dropOutputFile /]
    3. 

  3. [@pp.changeOutputFile name="mcuconf.h" /]
    4. 

  4. /*
    5. 

  5.     SPC5 HAL - Copyright (C) 2013 STMicroelectronics
    6. 

  6. 

  7.     Licensed under the Apache License, Version 2.0 (the "License");
    8. 

  8.     you may not use this file except in compliance with the License.
    9. 

  9.     You may obtain a copy of the License at
    10. 

  10. 

  11.         http://www.apache.org/licenses/LICENSE-2.0
    12. 

  12. 

  13.     Unless required by applicable law or agreed to in writing, software
    14. 

  14.     distributed under the License is distributed on an "AS IS" BASIS,
    15. 

  15.     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    16. 

  16.     See the License for the specific language governing permissions and
    17. 

  17.     limitations under the License.
    18. 

  18. */
    19. 

  19. 

  20. #ifndef _MCUCONF_H_
    21. 

  21. #define _MCUCONF_H_
    22. 

  22. 

  23. /*
    24. 

  24.  * SPC563Mxx drivers configuration.
    25. 

  25.  * The following settings override the default settings present in
    26. 

  26.  * the various device driver implementation headers.
    27. 

  27.  * Note that the settings for each driver only have effect if the whole
    28. 

  28.  * driver is enabled in halconf.h.
    29. 

  29.  *
    30. 

  30.  * IRQ priorities:
    31. 

  31.  * 1...15       Lowest...Highest.
    32. 

  32.  * DMA priorities:
    33. 

  33.  * 0...15       Highest...Lowest.
    34. 

  34.  */
    35. 

  35. 

  36. #define SPC563Mxx_MCUCONF
    37. 

  37. 

  38. /*
    39. 

  39.  * HAL driver system settings.
    40. 

  40.  */
    41. 

  41. #define SPC5_NO_INIT                        ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
    42. 

  42. #define SPC5_CLK_BYPASS                     ${conf.instance.initialization_settings.clock_bypass.value[0]?upper_case}
    43. 

  43. #define SPC5_ALLOW_OVERCLOCK                ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
    44. 

  44. #define SPC5_CLK_PREDIV_VALUE               ${conf.instance.initialization_settings.fmpll0_settings.prediv_value.value[0]}
    45. 

  45. #define SPC5_CLK_MFD_VALUE                  ${conf.instance.initialization_settings.fmpll0_settings.mfd_value.value[0]}
    46. 

  46. #define SPC5_CLK_RFD                        ${conf.instance.initialization_settings.fmpll0_settings.rfd_value.value[0]}
    47. 

  47. #define SPC5_FLASH_BIUCR                    (BIUCR_BANK1_TOO |              \
    48. 

  48.                                              BIUCR_MASTER4_PREFETCH |       \
    49. 

  49.                                              BIUCR_MASTER0_PREFETCH |       \
    50. 

  50.                                              BIUCR_DPFEN |                  \
    51. 

  51.                                              BIUCR_IPFEN |                  \
    52. 

  52.                                              BIUCR_PFLIM_ON_MISS |          \
    53. 

  53.                                              BIUCR_BFEN)
    54. 

  54. #define SPC5_EMIOS_GPRE_VALUE               ${conf.instance.initialization_settings.clocks.emios_global_prescaler.value[0]}
    55. 

  55. 

  56. /*
    57. 

  57.  * EDMA driver settings.
    58. 

  58.  */
    59. 

  59. #define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP1PRI(1) |           \
    60. 

  60.                                              EDMA_CR_GRP0PRI(0) |           \
    61. 

  61.                                              EDMA_CR_EMLM       |           \
    62. 

  62.                                              EDMA_CR_ERGA)
    63. 

  63. #define SPC5_EDMA_GROUP0_PRIORITIES         [#rt/]
    64. 

  64. [#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
    65. 

  65.   [#if channel_has_next]
    66. 

  66. ${channel.value[0]}, [#rt/]
    67. 

  67.   [#else]
    68. 

  68. ${channel.value[0]}
    69. 

  69.   [/#if]
    70. 

  70. [/#list]
    71. 

  71. #define SPC5_EDMA_GROUP1_PRIORITIES         [#rt/]
    72. 

  72. [#list conf.instance.edma_settings.group_1_channels_priorities.* as channel]
    73. 

  73.   [#if channel_has_next]
    74. 

  74. ${channel.value[0]}, [#rt/]
    75. 

  75.   [#else]
    76. 

  76. ${channel.value[0]}
    77. 

  77.   [/#if]
    78. 

  78. [/#list]
    79. 

  79. #define SPC5_EDMA_ERROR_IRQ_PRIO            12
    80. 

  80. #define SPC5_EDMA_ERROR_HANDLER()           osalSysHalt("DMA failure")
    81. 

  81. 

  82. /*
    83. 

  83.  * ADC driver settings.
    84. 

  84.  */
    85. 

  85. #define SPC5_ADC_USE_ADC0_Q0                ${conf.instance.eqadc_settings.fifo0.value[0]?upper_case}
    86. 

  86. #define SPC5_ADC_USE_ADC0_Q1                ${conf.instance.eqadc_settings.fifo1.value[0]?upper_case}
    87. 

  87. #define SPC5_ADC_USE_ADC0_Q2                ${conf.instance.eqadc_settings.fifo2.value[0]?upper_case}
    88. 

  88. #define SPC5_ADC_USE_ADC1_Q3                ${conf.instance.eqadc_settings.fifo3.value[0]?upper_case}
    89. 

  89. #define SPC5_ADC_USE_ADC1_Q4                ${conf.instance.eqadc_settings.fifo4.value[0]?upper_case}
    90. 

  90. #define SPC5_ADC_USE_ADC1_Q5                ${conf.instance.eqadc_settings.fifo5.value[0]?upper_case}
    91. 

  91. #define SPC5_ADC_FIFO0_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.eqadc_fifo0.value[0]}
    92. 

  92. #define SPC5_ADC_FIFO1_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.eqadc_fifo1.value[0]}
    93. 

  93. #define SPC5_ADC_FIFO2_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.eqadc_fifo2.value[0]}
    94. 

  94. #define SPC5_ADC_FIFO3_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.eqadc_fifo3.value[0]}
    95. 

  95. #define SPC5_ADC_FIFO4_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.eqadc_fifo4.value[0]}
    96. 

  96. #define SPC5_ADC_FIFO5_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.eqadc_fifo5.value[0]}
    97. 

  97. #define SPC5_ADC_CR_CLK_PS                  ADC_CR_CLK_PS(${conf.instance.eqadc_settings.divider.value[0]})
    98. 

  98. [#assign AN0 = conf.instance.eqadc_settings.an0.value[0]?upper_case?replace(" ", "_") /]
    99. 

  99. [#assign AN1 = conf.instance.eqadc_settings.an1.value[0]?upper_case?replace(" ", "_") /]
    100. 

  100. [#assign AN2 = conf.instance.eqadc_settings.an2.value[0]?upper_case?replace(" ", "_") /]
    101. 

  101. [#assign AN3 = conf.instance.eqadc_settings.an3.value[0]?upper_case?replace(" ", "_") /]
    102. 

  102. [#assign AN4 = conf.instance.eqadc_settings.an4.value[0]?upper_case?replace(" ", "_") /]
    103. 

  103. [#assign AN5 = conf.instance.eqadc_settings.an5.value[0]?upper_case?replace(" ", "_") /]
    104. 

  104. [#assign AN6 = conf.instance.eqadc_settings.an6.value[0]?upper_case?replace(" ", "_") /]
    105. 

  105. [#assign AN7 = conf.instance.eqadc_settings.an7.value[0]?upper_case?replace(" ", "_") /]
    106. 

  106. #define SPC5_ADC_PUDCR                      {ADC_PUDCR_${AN0},ADC_PUDCR_${AN1},ADC_PUDCR_${AN2},ADC_PUDCR_${AN3},ADC_PUDCR_${AN4},ADC_PUDCR_${AN5},ADC_PUDCR_${AN6},ADC_PUDCR_${AN7}}
    107. 

  107. 

  108. /*
    109. 

  109.  * SERIAL driver system settings.
    110. 

  110.  */
    111. 

  111. #define SPC5_USE_ESCIA                      ${(conf.instance.esci_settings.esci0.value[0] == "Serial")?string?upper_case}
    112. 

  112. #define SPC5_USE_ESCIB                      ${(conf.instance.esci_settings.esci1.value[0] == "Serial")?string?upper_case}
    113. 

  113. #define SPC5_ESCIA_PRIORITY                 ${conf.instance.irq_priority_settings.esci0.value[0]}
    114. 

  114. #define SPC5_ESCIB_PRIORITY                 ${conf.instance.irq_priority_settings.esci1.value[0]}
    115. 

  115. 

  116. /*
    117. 

  117.  * SPI driver system settings.
    118. 

  118.  */
    119. 

  119. #define SPC5_SPI_USE_DSPI1                  ${conf.instance.dspi_settings.dspi_b.value[0]?upper_case}
    120. 

  120. #define SPC5_SPI_USE_DSPI2                  ${conf.instance.dspi_settings.dspi_c.value[0]?upper_case}
    121. 

  121. #define SPC5_SPI_DMA_MODE                   SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
    122. 

  122. [#assign bs0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs0[0].@index[0]?trim?number] /]
    123. 

  123. [#assign bs1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs1[0].@index[0]?trim?number] /]
    124. 

  124. [#assign bs2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs2[0].@index[0]?trim?number] /]
    125. 

  125. [#assign bs3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs3[0].@index[0]?trim?number] /]
    126. 

  126. [#assign bs4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs4[0].@index[0]?trim?number] /]
    127. 

  127. [#assign bs5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_b___pcs5[0].@index[0]?trim?number] /]
    128. 

  128. #define SPC5_SPI_DSPI1_MCR                  (0${bs0 + bs1 + bs2 + bs3 + bs4 + bs5})
    129. 

  129. [#assign cs0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs0[0].@index[0]?trim?number] /]
    130. 

  130. [#assign cs1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs1[0].@index[0]?trim?number] /]
    131. 

  131. [#assign cs2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs2[0].@index[0]?trim?number] /]
    132. 

  132. [#assign cs3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs3[0].@index[0]?trim?number] /]
    133. 

  133. [#assign cs4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs4[0].@index[0]?trim?number] /]
    134. 

  134. [#assign cs5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_c___pcs5[0].@index[0]?trim?number] /]
    135. 

  135. #define SPC5_SPI_DSPI2_MCR                  (0${cs0 + cs1 + cs2 + cs3 + cs4 + cs5})
    136. 

  136. #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_b.value[0]}
    137. 

  137. #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_c.value[0]}
    138. 

  138. #define SPC5_SPI_DSPI1_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_b.value[0]}
    139. 

  139. #define SPC5_SPI_DSPI2_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_c.value[0]}
    140. 

  140. #define SPC5_SPI_DMA_ERROR_HOOK(spip)       ${conf.instance.dspi_settings.dma_error_hook.value[0]}
    141. 

  141. 

  142. /*
    143. 

  143.  * ICU driver system settings.
    144. 

  144.  */
    145. 

  145. #define SPC5_ICU_USE_EMIOS_CH0              ${(conf.instance.emios200_settings.emios_uc0.value[0] == "ICU")?string?upper_case}
    146. 

  146. #define SPC5_ICU_USE_EMIOS_CH1              ${(conf.instance.emios200_settings.emios_uc1.value[0] == "ICU")?string?upper_case}
    147. 

  147. #define SPC5_ICU_USE_EMIOS_CH2              ${(conf.instance.emios200_settings.emios_uc2.value[0] == "ICU")?string?upper_case}
    148. 

  148. #define SPC5_ICU_USE_EMIOS_CH3              ${(conf.instance.emios200_settings.emios_uc3.value[0] == "ICU")?string?upper_case}
    149. 

  149. #define SPC5_ICU_USE_EMIOS_CH4              ${(conf.instance.emios200_settings.emios_uc4.value[0] == "ICU")?string?upper_case}
    150. 

  150. #define SPC5_ICU_USE_EMIOS_CH5              ${(conf.instance.emios200_settings.emios_uc5.value[0] == "ICU")?string?upper_case}
    151. 

  151. #define SPC5_ICU_USE_EMIOS_CH6              ${(conf.instance.emios200_settings.emios_uc6.value[0] == "ICU")?string?upper_case}
    152. 

  152. #define SPC5_ICU_USE_EMIOS_CH8              ${(conf.instance.emios200_settings.emios_uc8.value[0] == "ICU")?string?upper_case}
    153. 

  153. #define SPC5_ICU_USE_EMIOS_CH9              ${(conf.instance.emios200_settings.emios_uc9.value[0] == "ICU")?string?upper_case}
    154. 

  154. #define SPC5_ICU_USE_EMIOS_CH10             ${(conf.instance.emios200_settings.emios_uc10.value[0] == "ICU")?string?upper_case}
    155. 

  155. #define SPC5_ICU_USE_EMIOS_CH11             ${(conf.instance.emios200_settings.emios_uc11.value[0] == "ICU")?string?upper_case}
    156. 

  156. #define SPC5_ICU_USE_EMIOS_CH12             ${(conf.instance.emios200_settings.emios_uc12.value[0] == "ICU")?string?upper_case}
    157. 

  157. #define SPC5_ICU_USE_EMIOS_CH13             ${(conf.instance.emios200_settings.emios_uc13.value[0] == "ICU")?string?upper_case}
    158. 

  158. #define SPC5_ICU_USE_EMIOS_CH14             ${(conf.instance.emios200_settings.emios_uc14.value[0] == "ICU")?string?upper_case}
    159. 

  159. #define SPC5_ICU_USE_EMIOS_CH15             ${(conf.instance.emios200_settings.emios_uc15.value[0] == "ICU")?string?upper_case}
    160. 

  160. #define SPC5_ICU_USE_EMIOS_CH23             ${(conf.instance.emios200_settings.emios_uc23.value[0] == "ICU")?string?upper_case}
    161. 

  161. 

  162. /*
    163. 

  163.  * PWM driver system settings.
    164. 

  164.  */
    165. 

  165. #define SPC5_PWM_USE_EMIOS_CH0              ${(conf.instance.emios200_settings.emios_uc0.value[0] == "PWM")?string?upper_case}
    166. 

  166. #define SPC5_PWM_USE_EMIOS_CH8              ${(conf.instance.emios200_settings.emios_uc8.value[0] == "PWM")?string?upper_case}
    167. 

  167. #define SPC5_PWM_USE_EMIOS_CH9              ${(conf.instance.emios200_settings.emios_uc9.value[0] == "PWM")?string?upper_case}
    168. 

  168. #define SPC5_PWM_USE_EMIOS_CH10             ${(conf.instance.emios200_settings.emios_uc10.value[0] == "PWM")?string?upper_case}
    169. 

  169. #define SPC5_PWM_USE_EMIOS_CH12             ${(conf.instance.emios200_settings.emios_uc12.value[0] == "PWM")?string?upper_case}
    170. 

  170. #define SPC5_PWM_USE_EMIOS_CH14             ${(conf.instance.emios200_settings.emios_uc14.value[0] == "PWM")?string?upper_case}
    171. 

  171. #define SPC5_PWM_USE_EMIOS_CH15             ${(conf.instance.emios200_settings.emios_uc15.value[0] == "PWM")?string?upper_case}
    172. 

  172. #define SPC5_PWM_USE_EMIOS_CH23             ${(conf.instance.emios200_settings.emios_uc23.value[0] == "PWM")?string?upper_case}
    173. 

  173. 

  174. /*
    175. 

  175.  * eMIOS channel priorities.
    176. 

  176.  */
    177. 

  177. #define SPC5_EMIOS_FLAG_F0_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc0.value[0]}
    178. 

  178. #define SPC5_EMIOS_FLAG_F1_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc1.value[0]}
    179. 

  179. #define SPC5_EMIOS_FLAG_F2_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc2.value[0]}
    180. 

  180. #define SPC5_EMIOS_FLAG_F3_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc3.value[0]}
    181. 

  181. #define SPC5_EMIOS_FLAG_F4_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc4.value[0]}
    182. 

  182. #define SPC5_EMIOS_FLAG_F5_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc5.value[0]}
    183. 

  183. #define SPC5_EMIOS_FLAG_F6_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc6.value[0]}
    184. 

  184. #define SPC5_EMIOS_FLAG_F8_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc8.value[0]}
    185. 

  185. #define SPC5_EMIOS_FLAG_F9_PRIORITY         ${conf.instance.irq_priority_settings.emios_uc9.value[0]}
    186. 

  186. #define SPC5_EMIOS_FLAG_F10_PRIORITY        ${conf.instance.irq_priority_settings.emios_uc10.value[0]}
    187. 

  187. #define SPC5_EMIOS_FLAG_F11_PRIORITY        ${conf.instance.irq_priority_settings.emios_uc11.value[0]}
    188. 

  188. #define SPC5_EMIOS_FLAG_F12_PRIORITY        ${conf.instance.irq_priority_settings.emios_uc12.value[0]}
    189. 

  189. #define SPC5_EMIOS_FLAG_F13_PRIORITY        ${conf.instance.irq_priority_settings.emios_uc13.value[0]}
    190. 

  190. #define SPC5_EMIOS_FLAG_F14_PRIORITY        ${conf.instance.irq_priority_settings.emios_uc14.value[0]}
    191. 

  191. #define SPC5_EMIOS_FLAG_F15_PRIORITY        ${conf.instance.irq_priority_settings.emios_uc15.value[0]}
    192. 

  192. #define SPC5_EMIOS_FLAG_F23_PRIORITY        ${conf.instance.irq_priority_settings.emios_uc23.value[0]}
    193. 

  193. 

  194. /*
    195. 

  195.  * CAN driver system settings.
    196. 

  196.  */
    197. 

  197. #define SPC5_CAN_USE_FILTERS                ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
    198. 

  198. 

  199. #define SPC5_CAN_USE_FLEXCAN0               ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
    200. 

  200. #define SPC5_CAN_FLEXCAN0_USE_EXT_CLK       ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
    201. 

  201. #define SPC5_CAN_FLEXCAN0_IRQ_PRIORITY      ${conf.instance.irq_priority_settings.flexcan0.value[0]}
    202. 

  202. #define SPC5_CAN_NUM_RX_MAILBOXES			${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
    203. 

  203. #define SPC5_CAN_NUM_TX_MAILBOXES			${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
    204. 

  204. 

  205. #define SPC5_CAN_USE_FLEXCAN1               ${conf.instance.flexcan_settings.flexcan1.value[0]?upper_case}
    206. 

  206. #define SPC5_CAN_FLEXCAN1_USE_EXT_CLK       ${conf.instance.flexcan_settings.flexcan1_use_external_clock.value[0]?upper_case}
    207. 

  207. #define SPC5_CAN_FLEXCAN1_IRQ_PRIORITY      ${conf.instance.irq_priority_settings.flexcan1.value[0]}
    208. 

  208. 

  209. #endif /* _MCUCONF_H_ */
    210.