Home Explore Help
Register Sign In
wangdan
/
watchrobot
1
0
Fork 0
Files Issues 0 Pull Requests 0 Wiki
Tree: d8d00aa3e7
Branches Tags
watchrobot
/
modules
/
ChibiOS
/
os
/
hal
/
ports
/
SPC5
/
SPC560Pxx
/
cfg
/
mcuconf.h.ftl

mcuconf.h.ftl 28 KB
History Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452 
  1. [#ftl]
    2. 

  2. 

  3. <#--
    4. 

  4.   -- Decodes a ME_xxx_MC register description node.
    5. 

  5.   -->
    6. 

  6. [#function decode_mc node]
    7. 

  7.   [#assign s = "" /]
    8. 

  8.   [#if node.pdo.value[0]?lower_case == "true"]
    9. 

  9.     [#assign s = s + " | SPC5_ME_MC_PDO" /]
    10. 

  10.   [/#if]
    11. 

  11.   [#if node.mvron.value[0]?lower_case == "true"]
    12. 

  12.     [#assign s = s + " | SPC5_ME_MC_MVRON" /]
    13. 

  13.   [/#if]
    14. 

  14.   [#assign n = node.dflaon.@index[0]?trim?number /]
    15. 

  15.   [#if n == 0]
    16. 

  16.     [#assign s = s + " | SPC5_ME_MC_DFLAON_NORMAL" /]
    17. 

  17.   [#elseif n == 1]
    18. 

  18.     [#assign s = s + " | SPC5_ME_MC_DFLAON_LP" /]
    19. 

  19.   [#else]
    20. 

  20.     [#assign s = s + " | SPC5_ME_MC_DFLAON_PD" /]
    21. 

  21.   [/#if]
    22. 

  22.   [#assign n = node.cflaon.@index[0]?trim?number /]
    23. 

  23.   [#if n == 0]
    24. 

  24.     [#assign s = s + " | SPC5_ME_MC_CFLAON_NORMAL" /]
    25. 

  25.   [#elseif n == 1]
    26. 

  26.     [#assign s = s + " | SPC5_ME_MC_CFLAON_LP" /]
    27. 

  27.   [#else]
    28. 

  28.     [#assign s = s + " | SPC5_ME_MC_CFLAON_PD" /]
    29. 

  29.   [/#if]
    30. 

  30.   [#if node.pll1on.value[0]?lower_case == "true"]
    31. 

  31.     [#assign s = s + " | SPC5_ME_MC_PLL1ON" /]
    32. 

  32.   [/#if]
    33. 

  33.   [#if node.pll0on.value[0]?lower_case == "true"]
    34. 

  34.     [#assign s = s + " | SPC5_ME_MC_PLL0ON" /]
    35. 

  35.   [/#if]
    36. 

  36.   [#if node.xosc0on.value[0]?lower_case == "true"]
    37. 

  37.     [#assign s = s + " | SPC5_ME_MC_XOSC0ON" /]
    38. 

  38.   [/#if]
    39. 

  39.   [#if node.ircon.value[0]?lower_case == "true"]
    40. 

  40.     [#assign s = s + " | SPC5_ME_MC_IRCON" /]
    41. 

  41.   [/#if]
    42. 

  42.   [#assign n = node.sysclk.@index[0]?trim?number /]
    43. 

  43.   [#if n == 0]
    44. 

  44.     [#assign s = s + " | SPC5_ME_MC_SYSCLK_IRC" /]
    45. 

  45.   [#elseif n == 1]
    46. 

  46.     [#assign s = s + " | SPC5_ME_MC_SYSCLK_XOSC" /]
    47. 

  47.   [#elseif n == 2]
    48. 

  48.     [#assign s = s + " | SPC5_ME_MC_SYSCLK_FMPLL0" /]
    49. 

  49.   [#elseif n == 3]
    50. 

  50.     [#assign s = s + " | SPC5_ME_MC_SYSCLK_FMPLL1" /]
    51. 

  51.   [#else]
    52. 

  52.     [#assign s = s + " | SPC5_ME_MC_SYSCLK_DISABLED" /]
    53. 

  53.   [/#if]
    54. 

  54.   [#return s]
    55. 

  55. [/#function]
    56. 

  56. 

  57. <#--
    58. 

  58.   -- Decodes a ME_RUN_PCx register description node.
    59. 

  59.   -->
    60. 

  60. [#function decode_runpc node]
    61. 

  61.   [#assign s = "" /]
    62. 

  62.   [#if node.safe.value[0]?lower_case == "true"]
    63. 

  63.     [#assign s = s + " | SPC5_ME_RUN_PC_SAFE" /]
    64. 

  64.   [/#if]
    65. 

  65.   [#if node.drun.value[0]?lower_case == "true"]
    66. 

  66.     [#assign s = s + " | SPC5_ME_RUN_PC_DRUN" /]
    67. 

  67.   [/#if]
    68. 

  68.   [#if node.run0.value[0]?lower_case == "true"]
    69. 

  69.     [#assign s = s + " | SPC5_ME_RUN_PC_RUN0" /]
    70. 

  70.   [/#if]
    71. 

  71.   [#if node.run1.value[0]?lower_case == "true"]
    72. 

  72.     [#assign s = s + " | SPC5_ME_RUN_PC_RUN1" /]
    73. 

  73.   [/#if]
    74. 

  74.   [#if node.run2.value[0]?lower_case == "true"]
    75. 

  75.     [#assign s = s + " | SPC5_ME_RUN_PC_RUN2" /]
    76. 

  76.   [/#if]
    77. 

  77.   [#if node.run3.value[0]?lower_case == "true"]
    78. 

  78.     [#assign s = s + " | SPC5_ME_RUN_PC_RUN3" /]
    79. 

  79.   [/#if]
    80. 

  80.   [#return s]
    81. 

  81. [/#function]
    82. 

  82. 

  83. <#--
    84. 

  84.   -- Decodes a ME_LP_PCx register description node.
    85. 

  85.   -->
    86. 

  86. [#function decode_lppc node]
    87. 

  87.   [#assign s = "" /]
    88. 

  88.   [#if node.halt0.value[0]?lower_case == "true"]
    89. 

  89.     [#assign s = s + " | SPC5_ME_LP_PC_HALT0" /]
    90. 

  90.   [/#if]
    91. 

  91.   [#if node.stop0.value[0]?lower_case == "true"]
    92. 

  92.     [#assign s = s + " | SPC5_ME_LP_PC_STOP0" /]
    93. 

  93.   [/#if]
    94. 

  94.   [#return s]
    95. 

  95. [/#function]
    96. 

  96. 

  97. [@pp.dropOutputFile /]
    98. 

  98. [@pp.changeOutputFile name="mcuconf.h" /]
    99. 

  99. /*
    100. 

  100.     SPC5 HAL - Copyright (C) 2013 STMicroelectronics
    101. 

  101. 

  102.     Licensed under the Apache License, Version 2.0 (the "License");
    103. 

  103.     you may not use this file except in compliance with the License.
    104. 

  104.     You may obtain a copy of the License at
    105. 

  105. 

  106.         http://www.apache.org/licenses/LICENSE-2.0
    107. 

  107. 

  108.     Unless required by applicable law or agreed to in writing, software
    109. 

  109.     distributed under the License is distributed on an "AS IS" BASIS,
    110. 

  110.     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    111. 

  111.     See the License for the specific language governing permissions and
    112. 

  112.     limitations under the License.
    113. 

  113. */
    114. 

  114. 

  115. #ifndef _MCUCONF_H_
    116. 

  116. #define _MCUCONF_H_
    117. 

  117. 

  118. /*
    119. 

  119.  * SPC560Pxx drivers configuration.
    120. 

  120.  * The following settings override the default settings present in
    121. 

  121.  * the various device driver implementation headers.
    122. 

  122.  * Note that the settings for each driver only have effect if the whole
    123. 

  123.  * driver is enabled in halconf.h.
    124. 

  124.  *
    125. 

  125.  * IRQ priorities:
    126. 

  126.  * 1...15       Lowest...Highest.
    127. 

  127.  * DMA priorities:
    128. 

  128.  * 0...15       Highest...Lowest.
    129. 

  129.  */
    130. 

  130. 

  131. #define SPC560Pxx_MCUCONF
    132. 

  132. 

  133. /*
    134. 

  134.  * HAL driver system settings.
    135. 

  135.  */
    136. 

  136. #define SPC5_NO_INIT                        ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
    137. 

  137. #define SPC5_ALLOW_OVERCLOCK                ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
    138. 

  138. #define SPC5_DISABLE_WATCHDOG               ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
    139. 

  139. #define SPC5_FMPLL0_IDF_VALUE               ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
    140. 

  140. #define SPC5_FMPLL0_NDIV_VALUE              ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
    141. 

  141. #define SPC5_FMPLL0_ODF                     ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
    142. 

  142. [#assign options = "" /]
    143. 

  143. [#if conf.instance.initialization_settings.fmpll0_settings.progressive_clock_switching.value[0]?lower_case == "true"]
    144. 

  144.   [#assign options = options + " | SPC5_FMPLL_EN_PLL_SW" /]
    145. 

  145. [/#if]
    146. 

  146. [#if conf.instance.initialization_settings.fmpll0_settings.mask_fail_output.value[0]?lower_case == "true"]
    147. 

  147.   [#assign options = options + " | SPC5_FMPLL_PLL_FAIL_MASK" /]
    148. 

  148. [/#if]
    149. 

  149. #define SPC5_FMPLL0_OPTIONS                 (0${options})
    150. 

  150. [#assign options = "" /]
    151. 

  151. [#if conf.instance.initialization_settings.fmpll0_settings.fm_enable.value[0]?lower_case == "true"]
    152. 

  152.   [#assign options = options + " | SPC5_FMPLL_FM_EN" /]
    153. 

  153.   [#if conf.instance.initialization_settings.fmpll0_settings.spread_type.@index[0]?trim?number != 0]
    154. 

  154.     [#assign options = options + " | SPC5_FMPLL_SPRD_SEL" /]
    155. 

  155.   [/#if]
    156. 

  156.   [#assign options = options + " | SPC5_FMPLL_MOD_PERIOD(" + conf.instance.initialization_settings.fmpll0_settings.modulation_period.value[0]?trim + ")" /]
    157. 

  157.   [#assign options = options + " | SPC5_FMPLL_INC_STEP(" + conf.instance.initialization_settings.fmpll0_settings.increment_step.value[0]?trim + ")" /]
    158. 

  158. [/#if]
    159. 

  159. #define SPC5_FMPLL0_MR_INIT                 (0${options})
    160. 

  160. #define SPC5_FMPLL1_IDF_VALUE               ${conf.instance.initialization_settings.fmpll1_settings.idf_value.value[0]}
    161. 

  161. #define SPC5_FMPLL1_NDIV_VALUE              ${conf.instance.initialization_settings.fmpll1_settings.ndiv_value.value[0]}
    162. 

  162. #define SPC5_FMPLL1_ODF                     ${conf.instance.initialization_settings.fmpll1_settings.odf_value.value[0]}
    163. 

  163. [#assign options = "" /]
    164. 

  164. [#if conf.instance.initialization_settings.fmpll1_settings.progressive_clock_switching.value[0]?lower_case == "true"]
    165. 

  165.   [#assign options = options + " | SPC5_FMPLL_EN_PLL_SW" /]
    166. 

  166. [/#if]
    167. 

  167. [#if conf.instance.initialization_settings.fmpll1_settings.mask_fail_output[0].value?lower_case == "true"]
    168. 

  168.   [#assign options = options + " | SPC5_FMPLL_PLL_FAIL_MASK" /]
    169. 

  169. [/#if]
    170. 

  170. #define SPC5_FMPLL1_OPTIONS                 (0${options})
    171. 

  171. [#assign options = "" /]
    172. 

  172. [#if conf.instance.initialization_settings.fmpll1_settings.fm_enable.value[0]?lower_case == "true"]
    173. 

  173.   [#assign options = options + " | SPC5_FMPLL_FM_EN" /]
    174. 

  174.   [#if conf.instance.initialization_settings.fmpll1_settings.spread_type.@index[0]?trim?number != 0]
    175. 

  175.     [#assign options = options + " | SPC5_FMPLL_SPRD_SEL" /]
    176. 

  176.   [/#if]
    177. 

  177.   [#assign options = options + " | SPC5_FMPLL_MOD_PERIOD(" + conf.instance.initialization_settings.fmpll1_settings.modulation_period.value[0]?trim + ")" /]
    178. 

  178.   [#assign options = options + " | SPC5_FMPLL_INC_STEP(" + conf.instance.initialization_settings.fmpll1_settings.increment_step.value[0]?trim + ")" /]
    179. 

  179. [/#if]
    180. 

  180. #define SPC5_FMPLL1_MR_INIT                 (0${options})
    181. 

  181. #define SPC5_CLKOUT_SRC                     SPC5_CGM_OCDS_SELCTL_${conf.instance.initialization_settings.clocks.clkout_clock_source.value[0]}
    182. 

  182. #define SPC5_CLKOUT_DIV_VALUE               ${conf.instance.initialization_settings.clocks.clkout_clock_divider.value[0]}
    183. 

  183. #define SPC5_AUX0CLK_SRC                    SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux0_clock_source.value[0]}
    184. 

  184. #define SPC5_MCONTROL_DIVIDER_VALUE         ${conf.instance.initialization_settings.clocks.motor_control_clock_divider.value[0]}
    185. 

  185. #define SPC5_FMPLL1_CLK_DIVIDER_VALUE       ${conf.instance.initialization_settings.clocks.fmpll1_div_clock_divider.value[0]}
    186. 

  186. #define SPC5_AUX2CLK_SRC                    SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux2_clock_source.value[0]}
    187. 

  187. #define SPC5_SP_CLK_DIVIDER_VALUE           ${conf.instance.initialization_settings.clocks.sp_clock_divider.value[0]}
    188. 

  188. #define SPC5_AUX3CLK_SRC                    SPC5_CGM_SS_${conf.instance.initialization_settings.clocks.aux3_clock_source.value[0]}
    189. 

  189. #define SPC5_FR_CLK_DIVIDER_VALUE           ${conf.instance.initialization_settings.clocks.fr_clock_divider.value[0]}
    190. 

  190. [#assign options = "SPC5_CMU_CSR_RCDIV(" + conf.instance.initialization_settings.cmu0_settings.rcdiv.@index[0]?trim + ")" /]
    191. 

  191. [#if conf.instance.initialization_settings.cmu0_settings.cme0.value[0]?lower_case == "true"]
    192. 

  192.   [#assign options = options + " | SPC5_CMU_CSR_CME" /]
    193. 

  193. [/#if]
    194. 

  194. #define SPC5_CMU0_CSR_INIT                  (${options})
    195. 

  195. #define SPC5_CMU0_HFREFR_INIT               ${conf.instance.initialization_settings.cmu0_settings.hfref.value[0]?trim}
    196. 

  196. #define SPC5_CMU0_LFREFR_INIT               ${conf.instance.initialization_settings.cmu0_settings.lfref.value[0]?trim}
    197. 

  197. #define SPC5_CMU0_MDR_INIT                  ${conf.instance.initialization_settings.cmu0_settings.md.value[0]?trim}
    198. 

  198. [#assign options = "" /]
    199. 

  199. [#if conf.instance.initialization_settings.cmu1_settings.cme1.value[0]?lower_case == "true"]
    200. 

  200.   [#assign options = options + "SPC5_CMU_CSR_CME" /]
    201. 

  201. [#else]
    202. 

  202.   [#assign options = "0" /]
    203. 

  203. [/#if]
    204. 

  204. #define SPC5_CMU1_CSR_INIT                  (${options})
    205. 

  205. #define SPC5_CMU1_HFREFR_INIT               ${conf.instance.initialization_settings.cmu1_settings.hfref.value[0]?trim}
    206. 

  206. #define SPC5_CMU1_LFREFR_INIT               ${conf.instance.initialization_settings.cmu1_settings.lfref.value[0]?trim}
    207. 

  207. [#assign options = "" /]
    208. 

  208. [#if conf.instance.initialization_settings.module_entry.run_modes.reset.value[0]?lower_case == "true"]
    209. 

  209.   [#assign options = options + " | SPC5_ME_ME_RESET" /]
    210. 

  210. [/#if]
    211. 

  211. [#if conf.instance.initialization_settings.module_entry.run_modes.safe.value[0]?lower_case == "true"]
    212. 

  212.   [#assign options = options + " | SPC5_ME_ME_SAFE" /]
    213. 

  213. [/#if]
    214. 

  214. [#if conf.instance.initialization_settings.module_entry.run_modes.drun.value[0]?lower_case == "true"]
    215. 

  215.   [#assign options = options + " | SPC5_ME_ME_DRUN" /]
    216. 

  216. [/#if]
    217. 

  217. [#if conf.instance.initialization_settings.module_entry.run_modes.run0.value[0]?lower_case == "true"]
    218. 

  218.   [#assign options = options + " | SPC5_ME_ME_RUN0" /]
    219. 

  219. [/#if]
    220. 

  220. [#if conf.instance.initialization_settings.module_entry.run_modes.run1.value[0]?lower_case == "true"]
    221. 

  221.   [#assign options = options + " | SPC5_ME_ME_RUN1" /]
    222. 

  222. [/#if]
    223. 

  223. [#if conf.instance.initialization_settings.module_entry.run_modes.run2.value[0]?lower_case == "true"]
    224. 

  224.   [#assign options = options + " | SPC5_ME_ME_RUN2" /]
    225. 

  225. [/#if]
    226. 

  226. [#if conf.instance.initialization_settings.module_entry.run_modes.run3.value[0]?lower_case == "true"]
    227. 

  227.   [#assign options = options + " | SPC5_ME_ME_RUN3" /]
    228. 

  228. [/#if]
    229. 

  229. [#if conf.instance.initialization_settings.module_entry.run_modes.halt0.value[0]?lower_case == "true"]
    230. 

  230.   [#assign options = options + " | SPC5_ME_ME_HALT0" /]
    231. 

  231. [/#if]
    232. 

  232. [#if conf.instance.initialization_settings.module_entry.run_modes.stop0.value[0]?lower_case == "true"]
    233. 

  233.   [#assign options = options + " | SPC5_ME_ME_STOP0" /]
    234. 

  234. [/#if]
    235. 

  235. #define SPC5_ME_ME_BITS                     (0${options})
    236. 

  236. #define SPC5_ME_SAFE_MC_BITS                (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.safe_state_settings)})
    237. 

  237. #define SPC5_ME_DRUN_MC_BITS                (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.drun_state_settings)})
    238. 

  238. #define SPC5_ME_RUN0_MC_BITS                (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run0_state_settings)})
    239. 

  239. #define SPC5_ME_RUN1_MC_BITS                (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run1_state_settings)})
    240. 

  240. #define SPC5_ME_RUN2_MC_BITS                (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run2_state_settings)})
    241. 

  241. #define SPC5_ME_RUN3_MC_BITS                (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.run3_state_settings)})
    242. 

  242. #define SPC5_ME_HALT0_MC_BITS               (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.halt0_state_settings)})
    243. 

  243. #define SPC5_ME_STOP0_MC_BITS               (0${decode_mc(conf.instance.initialization_settings.module_entry.run_modes.stop0_state_settings)})
    244. 

  244. #define SPC5_ME_RUN_PC3_BITS                (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc3)})
    245. 

  245. #define SPC5_ME_RUN_PC4_BITS                (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc4)})
    246. 

  246. #define SPC5_ME_RUN_PC5_BITS                (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc5)})
    247. 

  247. #define SPC5_ME_RUN_PC6_BITS                (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc6)})
    248. 

  248. #define SPC5_ME_RUN_PC7_BITS                (0${decode_runpc(conf.instance.initialization_settings.module_entry.peripherals_control__run_.pc7)})
    249. 

  249. #define SPC5_ME_LP_PC4_BITS                 (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc4)})
    250. 

  250. #define SPC5_ME_LP_PC5_BITS                 (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc5)})
    251. 

  251. #define SPC5_ME_LP_PC6_BITS                 (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc6)})
    252. 

  252. #define SPC5_ME_LP_PC7_BITS                 (0${decode_lppc(conf.instance.initialization_settings.module_entry.peripherals_control__low_power_.pc7)})
    253. 

  253. #define SPC5_FINAL_RUNMODE                  SPC5_RUNMODE_${conf.instance.initialization_settings.module_entry.final_run_mode.value[0]?trim}
    254. 

  254. #define SPC5_CLOCK_FAILURE_HOOK()           ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
    255. 

  255. 

  256. /*
    257. 

  257.  * EDMA driver settings.
    258. 

  258.  */
    259. 

  259. #define SPC5_EDMA_CR_SETTING                (EDMA_CR_GRP1PRI(1) |           \
    260. 

  260.                                              EDMA_CR_GRP0PRI(0) |           \
    261. 

  261.                                              EDMA_CR_EMLM       |           \
    262. 

  262.                                              EDMA_CR_ERGA)
    263. 

  263. #define SPC5_EDMA_GROUP0_PRIORITIES         [#rt/]
    264. 

  264. [#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
    265. 

  265.   [#if channel_has_next]
    266. 

  266. ${channel.value[0]}, [#rt/]
    267. 

  267.   [#else]
    268. 

  268. ${channel.value[0]}
    269. 

  269.   [/#if]
    270. 

  270. [/#list]
    271. 

  271. #define SPC5_EDMA_ERROR_IRQ_PRIO            12
    272. 

  272. #define SPC5_EDMA_ERROR_HANDLER()           osalSysHalt("DMA failure")
    273. 

  273. 

  274. /*
    275. 

  275.  * PWM driver system settings.
    276. 

  276.  */
    277. 

  277. [#assign pwm0_all_sm = conf.instance.flexpwm_settings.synchronized_flexpwm0.value[0]?upper_case /]
    278. 

  278. #define SPC5_PWM0_USE_SYNC_SMOD             ${pwm0_all_sm}
    279. 

  279. #define SPC5_PWM1_USE_SYNC_SMOD             FALSE
    280. 

  280. #define SPC5_PWM_USE_SMOD0                  ${conf.instance.flexpwm_settings.flexpwm0_sm0.value[0]?upper_case}
    281. 

  281. [#if pwm0_all_sm == "FALSE"]
    282. 

  282. #define SPC5_PWM_USE_SMOD1                  ${conf.instance.flexpwm_settings.flexpwm0_sm1.value[0]?upper_case}
    283. 

  283. #define SPC5_PWM_USE_SMOD2                  ${conf.instance.flexpwm_settings.flexpwm0_sm2.value[0]?upper_case}
    284. 

  284. #define SPC5_PWM_USE_SMOD3                  ${conf.instance.flexpwm_settings.flexpwm0_sm3.value[0]?upper_case}
    285. 

  285. [#else]
    286. 

  286. #define SPC5_PWM_USE_SMOD1                  TRUE
    287. 

  287. #define SPC5_PWM_USE_SMOD2                  TRUE
    288. 

  288. #define SPC5_PWM_USE_SMOD3                  TRUE
    289. 

  289. [/#if]
    290. 

  290. #define SPC5_PWM_SMOD0_PRIORITY             ${conf.instance.irq_priority_settings.flexpwm0_sm0.value[0]}
    291. 

  291. #define SPC5_PWM_SMOD1_PRIORITY             ${conf.instance.irq_priority_settings.flexpwm0_sm1.value[0]}
    292. 

  292. #define SPC5_PWM_SMOD2_PRIORITY             ${conf.instance.irq_priority_settings.flexpwm0_sm2.value[0]}
    293. 

  293. #define SPC5_PWM_SMOD3_PRIORITY             ${conf.instance.irq_priority_settings.flexpwm0_sm3.value[0]}
    294. 

  294. 

  295. /*
    296. 

  296.  * ICU driver system settings.
    297. 

  297.  */
    298. 

  298. #define SPC5_ICU_USE_SMOD0                  ${conf.instance.etimer_settings.etimer0_ch0.value[0]?upper_case}
    299. 

  299. #define SPC5_ICU_USE_SMOD1                  ${conf.instance.etimer_settings.etimer0_ch1.value[0]?upper_case}
    300. 

  300. #define SPC5_ICU_USE_SMOD2                  ${conf.instance.etimer_settings.etimer0_ch2.value[0]?upper_case}
    301. 

  301. #define SPC5_ICU_USE_SMOD3                  ${conf.instance.etimer_settings.etimer0_ch3.value[0]?upper_case}
    302. 

  302. #define SPC5_ICU_USE_SMOD4                  ${conf.instance.etimer_settings.etimer0_ch4.value[0]?upper_case}
    303. 

  303. #define SPC5_ICU_USE_SMOD5                  ${conf.instance.etimer_settings.etimer0_ch5.value[0]?upper_case}
    304. 

  304. #define SPC5_ICU_ETIMER0_PRIORITY           ${conf.instance.irq_priority_settings.etimer0.value[0]}
    305. 

  305. 

  306. #define SPC5_ICU_USE_SMOD6                  ${conf.instance.etimer_settings.etimer1_ch0.value[0]?upper_case}
    307. 

  307. #define SPC5_ICU_USE_SMOD7                  ${conf.instance.etimer_settings.etimer1_ch1.value[0]?upper_case}
    308. 

  308. #define SPC5_ICU_USE_SMOD8                  ${conf.instance.etimer_settings.etimer1_ch2.value[0]?upper_case}
    309. 

  309. #define SPC5_ICU_USE_SMOD9                  ${conf.instance.etimer_settings.etimer1_ch3.value[0]?upper_case}
    310. 

  310. #define SPC5_ICU_USE_SMOD10                 ${conf.instance.etimer_settings.etimer1_ch4.value[0]?upper_case}
    311. 

  311. #define SPC5_ICU_USE_SMOD11                 ${conf.instance.etimer_settings.etimer1_ch5.value[0]?upper_case}
    312. 

  312. #define SPC5_ICU_ETIMER1_PRIORITY           ${conf.instance.irq_priority_settings.etimer1.value[0]}
    313. 

  313. 

  314. /*
    315. 

  315.  * SERIAL driver system settings.
    316. 

  316.  */
    317. 

  317. #define SPC5_SERIAL_USE_LINFLEX0            ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
    318. 

  318. #define SPC5_SERIAL_USE_LINFLEX1            ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
    319. 

  319. #define SPC5_SERIAL_LINFLEX0_PRIORITY       ${conf.instance.irq_priority_settings.linflex0.value[0]}
    320. 

  320. #define SPC5_SERIAL_LINFLEX1_PRIORITY       ${conf.instance.irq_priority_settings.linflex1.value[0]}
    321. 

  321. 

  322. /*
    323. 

  323.  * SPI driver system settings.
    324. 

  324.  */
    325. 

  325. #define SPC5_SPI_USE_DSPI0                  ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
    326. 

  326. #define SPC5_SPI_USE_DSPI1                  ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
    327. 

  327. #define SPC5_SPI_USE_DSPI2                  ${conf.instance.dspi_settings.dspi_2.value[0]?upper_case}
    328. 

  328. #define SPC5_SPI_USE_DSPI3                  ${conf.instance.dspi_settings.dspi_3.value[0]?upper_case}
    329. 

  329. #define SPC5_SPI_USE_DSPI4                  ${conf.instance.dspi_settings.dspi_4.value[0]?upper_case}
    330. 

  330. #define SPC5_SPI_DMA_MODE                   SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
    331. 

  331. [#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
    332. 

  332. [#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
    333. 

  333. [#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
    334. 

  334. [#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
    335. 

  335. [#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
    336. 

  336. [#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
    337. 

  337. [#assign s6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs6[0].@index[0]?trim?number] /]
    338. 

  338. [#assign s7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs7[0].@index[0]?trim?number] /]
    339. 

  339. #define SPC5_SPI_DSPI0_MCR                  (0${s0 + s1 + s2 + s3 + s4 + s5 + s6 + s7})
    340. 

  340. [#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
    341. 

  341. [#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
    342. 

  342. [#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
    343. 

  343. [#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
    344. 

  344. [#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
    345. 

  345. [#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs5[0].@index[0]?trim?number] /]
    346. 

  346. [#assign s6 = [""," | SPC5_MCR_PCSIS6"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs6[0].@index[0]?trim?number] /]
    347. 

  347. [#assign s7 = [""," | SPC5_MCR_PCSIS7"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs7[0].@index[0]?trim?number] /]
    348. 

  348. #define SPC5_SPI_DSPI1_MCR                  (0${s0 + s1 + s2 + s3 + s4 + s5 + s6 + s7})
    349. 

  349. [#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs0[0].@index[0]?trim?number] /]
    350. 

  350. [#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs1[0].@index[0]?trim?number] /]
    351. 

  351. [#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs2[0].@index[0]?trim?number] /]
    352. 

  352. [#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_2___pcs3[0].@index[0]?trim?number] /]
    353. 

  353. #define SPC5_SPI_DSPI2_MCR                  (0${s0 + s1 + s2 + s3})
    354. 

  354. [#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs0[0].@index[0]?trim?number] /]
    355. 

  355. [#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs1[0].@index[0]?trim?number] /]
    356. 

  356. [#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs2[0].@index[0]?trim?number] /]
    357. 

  357. [#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_3___pcs3[0].@index[0]?trim?number] /]
    358. 

  358. #define SPC5_SPI_DSPI3_MCR                  (0${s0 + s1 + s2 + s3})
    359. 

  359. [#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs0[0].@index[0]?trim?number] /]
    360. 

  360. [#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs1[0].@index[0]?trim?number] /]
    361. 

  361. [#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs2[0].@index[0]?trim?number] /]
    362. 

  362. [#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_4___pcs3[0].@index[0]?trim?number] /]
    363. 

  363. #define SPC5_SPI_DSPI4_MCR                  (0${s0 + s1 + s2 + s3})
    364. 

  364. #define SPC5_SPI_DSPI0_TX1_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
    365. 

  365. #define SPC5_SPI_DSPI0_TX2_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
    366. 

  366. #define SPC5_SPI_DSPI0_RX_DMA_CH_ID         ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
    367. 

  367. #define SPC5_SPI_DSPI1_TX1_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
    368. 

  368. #define SPC5_SPI_DSPI1_TX2_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
    369. 

  369. #define SPC5_SPI_DSPI1_RX_DMA_CH_ID         ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
    370. 

  370. #define SPC5_SPI_DSPI2_TX1_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx1.value[0]}
    371. 

  371. #define SPC5_SPI_DSPI2_TX2_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi2_tx2.value[0]}
    372. 

  372. #define SPC5_SPI_DSPI2_RX_DMA_CH_ID         ${conf.instance.edma_mux_settings.dspi_channels.dspi2_rx.value[0]}
    373. 

  373. #define SPC5_SPI_DSPI3_TX1_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx1.value[0]}
    374. 

  374. #define SPC5_SPI_DSPI3_TX2_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi3_tx2.value[0]}
    375. 

  375. #define SPC5_SPI_DSPI3_RX_DMA_CH_ID         ${conf.instance.edma_mux_settings.dspi_channels.dspi3_rx.value[0]}
    376. 

  376. #define SPC5_SPI_DSPI4_TX1_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx1.value[0]}
    377. 

  377. #define SPC5_SPI_DSPI4_TX2_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi4_tx2.value[0]}
    378. 

  378. #define SPC5_SPI_DSPI4_RX_DMA_CH_ID         ${conf.instance.edma_mux_settings.dspi_channels.dspi4_rx.value[0]}
    379. 

  379. #define SPC5_SPI_DSPI0_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_0.value[0]}
    380. 

  380. #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_1.value[0]}
    381. 

  381. #define SPC5_SPI_DSPI2_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_2.value[0]}
    382. 

  382. #define SPC5_SPI_DSPI3_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_3.value[0]}
    383. 

  383. #define SPC5_SPI_DSPI4_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_4.value[0]}
    384. 

  384. #define SPC5_SPI_DSPI0_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_0.value[0]}
    385. 

  385. #define SPC5_SPI_DSPI1_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_1.value[0]}
    386. 

  386. #define SPC5_SPI_DSPI2_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_2.value[0]}
    387. 

  387. #define SPC5_SPI_DSPI3_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_3.value[0]}
    388. 

  388. #define SPC5_SPI_DSPI4_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_4.value[0]}
    389. 

  389. #define SPC5_SPI_DMA_ERROR_HOOK(spip)       ${conf.instance.dspi_settings.dma_error_hook.value[0]}
    390. 

  390. 

  391. /*
    392. 

  392.  * CAN driver system settings.
    393. 

  393.  */
    394. 

  394. #define SPC5_CAN_USE_FILTERS                ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
    395. 

  395. 

  396. #define SPC5_CAN_USE_FLEXCAN0               ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
    397. 

  397. #define SPC5_CAN_FLEXCAN0_USE_EXT_CLK       ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
    398. 

  398. #define SPC5_CAN_FLEXCAN0_PRIORITY          ${conf.instance.irq_priority_settings.flexcan0.value[0]}
    399. 

  399. #define SPC5_CAN_NUM_RX_MAILBOXES			${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
    400. 

  400. #define SPC5_CAN_NUM_TX_MAILBOXES			${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
    401. 

  401. #define SPC5_CAN_FLEXCAN0_START_PCTL        (SPC5_ME_PCTL_RUN(1) |          \
    402. 

  402.                                              SPC5_ME_PCTL_LP(2))
    403. 

  403. #define SPC5_CAN_FLEXCAN0_STOP_PCTL         (SPC5_ME_PCTL_RUN(0) |          \
    404. 

  404.                                              SPC5_ME_PCTL_LP(0))
    405. 

  405. 

  406. /*
    407. 

  407. * ADC driver system settings.
    408. 

  408. */
    409. 

  409. [#if conf.instance.adc_settings.adc0_clock_divider.value[0] == "Peripheral clock frequency"]
    410. 

  410.   [#assign clk_f0 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
    411. 

  411. [#else]
    412. 

  412.   [#assign clk_f0 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
    413. 

  413. [/#if]
    414. 

  414. 

  415. [#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
    416. 

  416.   [#assign dma_mode = "SPC5_ADC_DMA_ON"]
    417. 

  417. [#else]
    418. 

  418.   [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
    419. 

  419. [/#if]
    420. 

  420. 

  421. #define SPC5_ADC_DMA_MODE                   ${dma_mode}
    422. 

  422. 

  423. #define SPC5_ADC_USE_ADC0                   ${conf.instance.adc_settings.adc0.value[0]?upper_case}
    424. 

  424. #define SPC5_ADC_ADC0_CLK_FREQUENCY         ${clk_f0}
    425. 

  425. #define SPC5_ADC_ADC0_AUTO_CLOCK_OFF        ${conf.instance.adc_settings.adc0_auto_clock_off_mode.value[0]?upper_case}
    426. 

  426. #define SPC5_ADC_ADC0_WD_PRIORITY           ${conf.instance.irq_priority_settings.adc0.value[0]}
    427. 

  427. #define SPC5_ADC_ADC0_EOC_PRIORITY          SPC5_ADC_ADC0_WD_PRIORITY
    428. 

  428. #define SPC5_ADC_ADC0_DMA_CH_ID             ${conf.instance.edma_mux_settings.adc_channels.adc0.value[0]}
    429. 

  429. #define SPC5_ADC_ADC0_DMA_IRQ_PRIO          ${conf.instance.irq_priority_settings.adc0.value[0]}
    430. 

  430. #define SPC5_ADC_ADC0_START_PCTL            (SPC5_ME_PCTL_RUN(1) |          \
    431. 

  431.                                              SPC5_ME_PCTL_LP(2))
    432. 

  432. #define SPC5_ADC_ADC0_STOP_PCTL             (SPC5_ME_PCTL_RUN(0) |          \
    433. 

  433.                                              SPC5_ME_PCTL_LP(0))
    434. 

  434. 

  435. [#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
    436. 

  436.   [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
    437. 

  437. [#else]
    438. 

  438.   [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
    439. 

  439. [/#if]
    440. 

  440. #define SPC5_ADC_USE_ADC1                   ${conf.instance.adc_settings.adc1.value[0]?upper_case}
    441. 

  441. #define SPC5_ADC_ADC1_CLK_FREQUENCY         ${clk_f1}
    442. 

  442. #define SPC5_ADC_ADC1_AUTO_CLOCK_OFF        ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
    443. 

  443. #define SPC5_ADC_ADC1_WD_PRIORITY           ${conf.instance.irq_priority_settings.adc1.value[0]}
    444. 

  444. #define SPC5_ADC_ADC1_EOC_PRIORITY          SPC5_ADC_ADC1_WD_PRIORITY
    445. 

  445. #define SPC5_ADC_ADC1_DMA_CH_ID             ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
    446. 

  446. #define SPC5_ADC_ADC1_DMA_IRQ_PRIO          ${conf.instance.irq_priority_settings.adc1.value[0]}
    447. 

  447. #define SPC5_ADC_ADC1_START_PCTL            (SPC5_ME_PCTL_RUN(1) |          \
    448. 

  448.                                              SPC5_ME_PCTL_LP(2))
    449. 

  449. #define SPC5_ADC_ADC1_STOP_PCTL             (SPC5_ME_PCTL_RUN(0) |          \
    450. 

  450.                                              SPC5_ME_PCTL_LP(0))
    451. 

  451. 

  452. #endif /* _MCUCONF_H_ */
    453.