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mcuconf.h.ftl

mcuconf.h.ftl 12 KB
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  1. [#ftl]
    2. 

  2. [@pp.dropOutputFile /]
    3. 

  3. [@pp.changeOutputFile name="mcuconf.h" /]
    4. 

  4. /*
    5. 

  5.     SPC5 HAL - Copyright (C) 2013 STMicroelectronics
    6. 

  6. 

  7.     Licensed under the Apache License, Version 2.0 (the "License");
    8. 

  8.     you may not use this file except in compliance with the License.
    9. 

  9.     You may obtain a copy of the License at
    10. 

  10. 

  11.         http://www.apache.org/licenses/LICENSE-2.0
    12. 

  12. 

  13.     Unless required by applicable law or agreed to in writing, software
    14. 

  14.     distributed under the License is distributed on an "AS IS" BASIS,
    15. 

  15.     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
    16. 

  16.     See the License for the specific language governing permissions and
    17. 

  17.     limitations under the License.
    18. 

  18. */
    19. 

  19. 

  20. #ifndef _MCUCONF_H_
    21. 

  21. #define _MCUCONF_H_
    22. 

  22. 

  23. /*
    24. 

  24.  * SPC560B/Cxx drivers configuration.
    25. 

  25.  * The following settings override the default settings present in
    26. 

  26.  * the various device driver implementation headers.
    27. 

  27.  * Note that the settings for each driver only have effect if the whole
    28. 

  28.  * driver is enabled in halconf.h.
    29. 

  29.  *
    30. 

  30.  * IRQ priorities:
    31. 

  31.  * 1...15       Lowest...Highest.
    32. 

  32.  * DMA priorities:
    33. 

  33.  * 0...15       Highest...Lowest.
    34. 

  34.  */
    35. 

  35. 

  36. #define SPC560Dxx_MCUCONF
    37. 

  37. 

  38. /*
    39. 

  39.  * HAL driver system settings.
    40. 

  40.  */
    41. 

  41. #define SPC5_NO_INIT                        ${conf.instance.initialization_settings.do_not_init.value[0]?upper_case}
    42. 

  42. #define SPC5_ALLOW_OVERCLOCK                ${conf.instance.initialization_settings.allow_overclocking.value[0]?upper_case}
    43. 

  43. #define SPC5_DISABLE_WATCHDOG               ${conf.instance.initialization_settings.disable_watchdog.value[0]?upper_case}
    44. 

  44. #define SPC5_FMPLL0_IDF_VALUE               ${conf.instance.initialization_settings.fmpll0_settings.idf_value.value[0]}
    45. 

  45. #define SPC5_FMPLL0_NDIV_VALUE              ${conf.instance.initialization_settings.fmpll0_settings.ndiv_value.value[0]}
    46. 

  46. #define SPC5_FMPLL0_ODF                     ${conf.instance.initialization_settings.fmpll0_settings.odf_value.value[0]}
    47. 

  47. #define SPC5_XOSCDIV_VALUE                  ${conf.instance.initialization_settings.clocks.fxosc_divider.value[0]}
    48. 

  48. #define SPC5_IRCDIV_VALUE                   ${conf.instance.initialization_settings.clocks.firc_divider.value[0]}
    49. 

  49. #define SPC5_PERIPHERAL1_CLK_DIV_VALUE      ${conf.instance.initialization_settings.clocks.peripheral_set_1_clock_divider.value[0]}
    50. 

  50. #define SPC5_PERIPHERAL2_CLK_DIV_VALUE      ${conf.instance.initialization_settings.clocks.peripheral_set_2_clock_divider.value[0]}
    51. 

  51. #define SPC5_PERIPHERAL3_CLK_DIV_VALUE      ${conf.instance.initialization_settings.clocks.peripheral_set_3_clock_divider.value[0]}
    52. 

  52. #define SPC5_CLOCK_FAILURE_HOOK()           ${conf.instance.initialization_settings.clocks.clock_failure_hook.value[0]}
    53. 

  53. 

  54. #define SPC5_EMIOS0_GPRE_VALUE              ${conf.instance.initialization_settings.clocks.emios0_global_prescaler.value[0]?number}
    55. 

  55. 

  56. /*
    57. 

  57.  * EDMA driver settings.
    58. 

  58.  */
    59. 

  59. #define SPC5_EDMA_CR_SETTING                (EDMA_CR_EMLM)
    60. 

  60. #define SPC5_EDMA_GROUP0_PRIORITIES         [#rt/]
    61. 

  61. [#list conf.instance.edma_settings.group_0_channels_priorities.* as channel]
    62. 

  62.   [#if channel_has_next]
    63. 

  63. ${channel.value[0]}, [#rt/]
    64. 

  64.   [#else]
    65. 

  65. ${channel.value[0]}
    66. 

  66.   [/#if]
    67. 

  67. [/#list]
    68. 

  68. #define SPC5_EDMA_ERROR_IRQ_PRIO            12
    69. 

  69. #define SPC5_EDMA_ERROR_HANDLER()           osalSysHalt("DMA failure")
    70. 

  70. 

  71. /*
    72. 

  72.  * SERIAL driver system settings.
    73. 

  73.  */
    74. 

  74. #define SPC5_SERIAL_USE_LINFLEX0            ${(conf.instance.linflex_settings.linflex0.value[0] == "Serial")?string?upper_case}
    75. 

  75. #define SPC5_SERIAL_USE_LINFLEX1            ${(conf.instance.linflex_settings.linflex1.value[0] == "Serial")?string?upper_case}
    76. 

  76. #define SPC5_SERIAL_USE_LINFLEX2            ${(conf.instance.linflex_settings.linflex2.value[0] == "Serial")?string?upper_case}
    77. 

  77. #define SPC5_SERIAL_LINFLEX0_PRIORITY       ${conf.instance.irq_priority_settings.linflex0.value[0]}
    78. 

  78. #define SPC5_SERIAL_LINFLEX1_PRIORITY       ${conf.instance.irq_priority_settings.linflex1.value[0]}
    79. 

  79. #define SPC5_SERIAL_LINFLEX2_PRIORITY       ${conf.instance.irq_priority_settings.linflex2.value[0]}
    80. 

  80. 

  81. /*
    82. 

  82.  * SPI driver system settings.
    83. 

  83.  */
    84. 

  84. #define SPC5_SPI_USE_DSPI0                  ${conf.instance.dspi_settings.dspi_0.value[0]?upper_case}
    85. 

  85. #define SPC5_SPI_USE_DSPI1                  ${conf.instance.dspi_settings.dspi_1.value[0]?upper_case}
    86. 

  86. #define SPC5_SPI_DMA_MODE                   SPC5_SPI_DMA_${conf.instance.dspi_settings.dma_mode.value[0]?upper_case?replace(" ", "_")}
    87. 

  87. [#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs0[0].@index[0]?trim?number] /]
    88. 

  88. [#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs1[0].@index[0]?trim?number] /]
    89. 

  89. [#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs2[0].@index[0]?trim?number] /]
    90. 

  90. [#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs3[0].@index[0]?trim?number] /]
    91. 

  91. [#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs4[0].@index[0]?trim?number] /]
    92. 

  92. [#assign s5 = [""," | SPC5_MCR_PCSIS5"][conf.instance.dspi_settings.inactive_states.dspi_0___pcs5[0].@index[0]?trim?number] /]
    93. 

  93. #define SPC5_SPI_DSPI0_MCR                  (0${s0 + s1 + s2 + s3 + s4 + s5})
    94. 

  94. [#assign s0 = [""," | SPC5_MCR_PCSIS0"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs0[0].@index[0]?trim?number] /]
    95. 

  95. [#assign s1 = [""," | SPC5_MCR_PCSIS1"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs1[0].@index[0]?trim?number] /]
    96. 

  96. [#assign s2 = [""," | SPC5_MCR_PCSIS2"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs2[0].@index[0]?trim?number] /]
    97. 

  97. [#assign s3 = [""," | SPC5_MCR_PCSIS3"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs3[0].@index[0]?trim?number] /]
    98. 

  98. [#assign s4 = [""," | SPC5_MCR_PCSIS4"][conf.instance.dspi_settings.inactive_states.dspi_1___pcs4[0].@index[0]?trim?number] /]
    99. 

  99. #define SPC5_SPI_DSPI1_MCR                  (0${s0 + s1 + s2 + s3 + s4})
    100. 

  100. #define SPC5_SPI_DSPI0_TX1_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx1.value[0]}
    101. 

  101. #define SPC5_SPI_DSPI0_TX2_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi0_tx2.value[0]}
    102. 

  102. #define SPC5_SPI_DSPI0_RX_DMA_CH_ID         ${conf.instance.edma_mux_settings.dspi_channels.dspi0_rx.value[0]}
    103. 

  103. #define SPC5_SPI_DSPI1_TX1_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx1.value[0]}
    104. 

  104. #define SPC5_SPI_DSPI1_TX2_DMA_CH_ID        ${conf.instance.edma_mux_settings.dspi_channels.dspi1_tx2.value[0]}
    105. 

  105. #define SPC5_SPI_DSPI1_RX_DMA_CH_ID         ${conf.instance.edma_mux_settings.dspi_channels.dspi1_rx.value[0]}
    106. 

  106. #define SPC5_SPI_DSPI0_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_0.value[0]}
    107. 

  107. #define SPC5_SPI_DSPI1_DMA_IRQ_PRIO         ${conf.instance.irq_priority_settings.dspi_1.value[0]}
    108. 

  108. #define SPC5_SPI_DSPI0_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_0.value[0]}
    109. 

  109. #define SPC5_SPI_DSPI1_IRQ_PRIO             ${conf.instance.irq_priority_settings.dspi_1.value[0]}
    110. 

  110. #define SPC5_SPI_DMA_ERROR_HOOK(spip)       ${conf.instance.dspi_settings.dma_error_hook.value[0]}
    111. 

  111. 

  112. /*
    113. 

  113.  * ICU-PWM driver system settings.
    114. 

  114.  */
    115. 

  115. #define SPC5_ICU_USE_EMIOS0_CH0             ${conf.instance.emios_settings.emios0_ch0.value[0]?upper_case}
    116. 

  116. #define SPC5_ICU_USE_EMIOS0_CH1             ${conf.instance.emios_settings.emios0_ch1.value[0]?upper_case}
    117. 

  117. #define SPC5_ICU_USE_EMIOS0_CH2             ${conf.instance.emios_settings.emios0_ch2.value[0]?upper_case}
    118. 

  118. #define SPC5_ICU_USE_EMIOS0_CH3             ${conf.instance.emios_settings.emios0_ch3.value[0]?upper_case}
    119. 

  119. #define SPC5_ICU_USE_EMIOS0_CH4             ${conf.instance.emios_settings.emios0_ch4.value[0]?upper_case}
    120. 

  120. #define SPC5_ICU_USE_EMIOS0_CH5             ${conf.instance.emios_settings.emios0_ch5.value[0]?upper_case}
    121. 

  121. #define SPC5_ICU_USE_EMIOS0_CH6             ${conf.instance.emios_settings.emios0_ch6.value[0]?upper_case}
    122. 

  122. #define SPC5_ICU_USE_EMIOS0_CH7             ${conf.instance.emios_settings.emios0_ch7.value[0]?upper_case}
    123. 

  123. #define SPC5_ICU_USE_EMIOS0_CH24            ${conf.instance.emios_settings.emios0_ch24.value[0]?upper_case}
    124. 

  124. 

  125. #define SPC5_PWM_USE_EMIOS0_GROUP0          ${conf.instance.emios_settings.emios0_group0.value[0]?upper_case}
    126. 

  126. #define SPC5_PWM_USE_EMIOS0_GROUP1          ${conf.instance.emios_settings.emios0_group1.value[0]?upper_case}
    127. 

  127. 

  128. #define SPC5_EMIOS0_GFR_F0F1_PRIORITY       ${conf.instance.irq_priority_settings.emios0_uc0.value[0]}
    129. 

  129. #define SPC5_EMIOS0_GFR_F2F3_PRIORITY       ${conf.instance.irq_priority_settings.emios0_uc1.value[0]}
    130. 

  130. #define SPC5_EMIOS0_GFR_F4F5_PRIORITY       ${conf.instance.irq_priority_settings.emios0_uc2.value[0]}
    131. 

  131. #define SPC5_EMIOS0_GFR_F6F7_PRIORITY       ${conf.instance.irq_priority_settings.emios0_uc3.value[0]}
    132. 

  132. #define SPC5_EMIOS0_GFR_F8F9_PRIORITY       ${conf.instance.irq_priority_settings.emios0_uc4.value[0]}
    133. 

  133. #define SPC5_EMIOS0_GFR_F10F11_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc5.value[0]}
    134. 

  134. #define SPC5_EMIOS0_GFR_F12F13_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc6.value[0]}
    135. 

  135. #define SPC5_EMIOS0_GFR_F14F15_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc7.value[0]}
    136. 

  136. #define SPC5_EMIOS0_GFR_F16F17_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc8.value[0]}
    137. 

  137. #define SPC5_EMIOS0_GFR_F18F19_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc9.value[0]}
    138. 

  138. #define SPC5_EMIOS0_GFR_F20F21_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc10.value[0]}
    139. 

  139. #define SPC5_EMIOS0_GFR_F22F23_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc11.value[0]}
    140. 

  140. #define SPC5_EMIOS0_GFR_F24F25_PRIORITY     ${conf.instance.irq_priority_settings.emios0_uc12.value[0]}
    141. 

  141. 

  142. #define SPC5_EMIOS0_START_PCTL              (SPC5_ME_PCTL_RUN(1) |          \
    143. 

  143.                                              SPC5_ME_PCTL_LP(2))
    144. 

  144. #define SPC5_EMIOS0_STOP_PCTL               (SPC5_ME_PCTL_RUN(0) |          \
    145. 

  145.                                              SPC5_ME_PCTL_LP(0))
    146. 

  146. 

  147. /*
    148. 

  148.  * CAN driver system settings.
    149. 

  149.  */
    150. 

  150. #define SPC5_CAN_USE_FILTERS                ${conf.instance.flexcan_settings.flexcan_enable_filters.value[0]?upper_case}
    151. 

  151. 

  152. #define SPC5_CAN_USE_FLEXCAN0               ${conf.instance.flexcan_settings.flexcan0.value[0]?upper_case}
    153. 

  153. #define SPC5_CAN_FLEXCAN0_USE_EXT_CLK       ${conf.instance.flexcan_settings.flexcan0_use_external_clock.value[0]?upper_case}
    154. 

  154. #define SPC5_CAN_FLEXCAN0_PRIORITY          ${conf.instance.irq_priority_settings.flexcan0.value[0]}
    155. 

  155. #define SPC5_CAN_NUM_RX_MAILBOXES			${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_rx_mailboxes.value[0]}
    156. 

  156. #define SPC5_CAN_NUM_TX_MAILBOXES			${conf.instance.flexcan_settings.can_configurations.mailboxes_configuration.number_of_tx_mailboxes.value[0]}
    157. 

  157. #define SPC5_CAN_FLEXCAN0_START_PCTL        (SPC5_ME_PCTL_RUN(1) |          \
    158. 

  158.                                              SPC5_ME_PCTL_LP(2))
    159. 

  159. #define SPC5_CAN_FLEXCAN0_STOP_PCTL         (SPC5_ME_PCTL_RUN(0) |          \
    160. 

  160.                                              SPC5_ME_PCTL_LP(0))
    161. 

  161. 

  162. /*
    163. 

  163. * ADC driver system settings.
    164. 

  164. */
    165. 

  165. [#if conf.instance.adc_settings.adc1_clock_divider.value[0] == "Peripheral clock frequency"]
    166. 

  166.   [#assign clk_f1 = "PERIPHERAL_SET_CLOCK_FREQUENCY"]
    167. 

  167. [#else]
    168. 

  168.   [#assign clk_f1 = "HALF_PERIPHERAL_SET_CLOCK_FREQUENCY"]
    169. 

  169. [/#if]
    170. 

  170. 

  171. [#if conf.instance.adc_settings.dma_mode.value[0] == "true" ]
    172. 

  172.   [#assign dma_mode = "SPC5_ADC_DMA_ON"]
    173. 

  173. [#else]
    174. 

  174.   [#assign dma_mode = "SPC5_ADC_DMA_OFF"]
    175. 

  175. [/#if]
    176. 

  176. 

  177. #define SPC5_ADC_DMA_MODE                   ${dma_mode}
    178. 

  178. 

  179. #define SPC5_ADC_USE_ADC1                   ${conf.instance.adc_settings.adc1.value[0]?upper_case}
    180. 

  180. #define SPC5_ADC_ADC1_CLK_FREQUENCY         ${clk_f1}
    181. 

  181. #define SPC5_ADC_ADC1_AUTO_CLOCK_OFF        ${conf.instance.adc_settings.adc1_auto_clock_off_mode.value[0]?upper_case}
    182. 

  182. #define SPC5_ADC_ADC1_WD_PRIORITY           ${conf.instance.irq_priority_settings.adc1.value[0]}
    183. 

  183. #define SPC5_ADC_ADC1_EOC_PRIORITY          SPC5_ADC_ADC1_WD_PRIORITY
    184. 

  184. #define SPC5_ADC_ADC1_DMA_CH_ID             ${conf.instance.edma_mux_settings.adc_channels.adc1.value[0]}
    185. 

  185. #define SPC5_ADC_ADC1_DMA_IRQ_PRIO          ${conf.instance.irq_priority_settings.adc1.value[0]}
    186. 

  186. #define SPC5_ADC_ADC1_START_PCTL            (SPC5_ME_PCTL_RUN(1) |          \
    187. 

  187.                                              SPC5_ME_PCTL_LP(2))
    188. 

  188. #define SPC5_ADC_ADC1_STOP_PCTL             (SPC5_ME_PCTL_RUN(0) |          \
    189. 

  189.                                              SPC5_ME_PCTL_LP(0))
    190. 

  190. 

  191. #endif /* _MCUCONF_H_ */
    192.