mcuconf.h 7.5 KB

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  1. /*
  2. ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
  3. Licensed under the Apache License, Version 2.0 (the "License");
  4. you may not use this file except in compliance with the License.
  5. You may obtain a copy of the License at
  6. http://www.apache.org/licenses/LICENSE-2.0
  7. Unless required by applicable law or agreed to in writing, software
  8. distributed under the License is distributed on an "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  10. See the License for the specific language governing permissions and
  11. limitations under the License.
  12. */
  13. #ifndef MCUCONF_H
  14. #define MCUCONF_H
  15. /*
  16. * STM32F0xx drivers configuration.
  17. * The following settings override the default settings present in
  18. * the various device driver implementation headers.
  19. * Note that the settings for each driver only have effect if the whole
  20. * driver is enabled in halconf.h.
  21. *
  22. * IRQ priorities:
  23. * 3...0 Lowest...Highest.
  24. *
  25. * DMA priorities:
  26. * 0...3 Lowest...Highest.
  27. */
  28. #define STM32F0xx_MCUCONF
  29. /*
  30. * HAL driver system settings.
  31. */
  32. #define STM32_NO_INIT FALSE
  33. #define STM32_PVD_ENABLE FALSE
  34. #define STM32_PLS STM32_PLS_LEV0
  35. #define STM32_HSI_ENABLED TRUE
  36. #define STM32_HSI14_ENABLED TRUE
  37. #define STM32_LSI_ENABLED TRUE
  38. #define STM32_HSE_ENABLED FALSE
  39. #define STM32_LSE_ENABLED FALSE
  40. #define STM32_SW STM32_SW_PLL
  41. #define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
  42. #define STM32_PREDIV_VALUE 1
  43. #define STM32_PLLMUL_VALUE 12
  44. #define STM32_HPRE STM32_HPRE_DIV1
  45. #define STM32_PPRE STM32_PPRE_DIV1
  46. #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
  47. #define STM32_MCOPRE STM32_MCOPRE_DIV1
  48. #define STM32_PLLNODIV STM32_PLLNODIV_DIV2
  49. #define STM32_USBSW STM32_USBSW_HSI48
  50. #define STM32_CECSW STM32_CECSW_HSI
  51. #define STM32_I2C1SW STM32_I2C1SW_HSI
  52. #define STM32_USART1SW STM32_USART1SW_PCLK
  53. #define STM32_RTCSEL STM32_RTCSEL_LSI
  54. /*
  55. * IRQ system settings.
  56. */
  57. #define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3
  58. #define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3
  59. #define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3
  60. #define STM32_IRQ_EXTI16_IRQ_PRIORITY 3
  61. #define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3
  62. #define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3
  63. /*
  64. * ADC driver system settings.
  65. */
  66. #define STM32_ADC_USE_ADC1 FALSE
  67. #define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
  68. #define STM32_ADC_ADC1_DMA_PRIORITY 2
  69. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
  70. #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
  71. /*
  72. * GPT driver system settings.
  73. */
  74. #define STM32_GPT_USE_TIM1 FALSE
  75. #define STM32_GPT_USE_TIM2 FALSE
  76. #define STM32_GPT_USE_TIM3 FALSE
  77. #define STM32_GPT_USE_TIM14 FALSE
  78. #define STM32_GPT_TIM1_IRQ_PRIORITY 2
  79. #define STM32_GPT_TIM2_IRQ_PRIORITY 2
  80. #define STM32_GPT_TIM3_IRQ_PRIORITY 2
  81. #define STM32_GPT_TIM14_IRQ_PRIORITY 2
  82. /*
  83. * I2C driver system settings.
  84. */
  85. #define STM32_I2C_USE_I2C1 FALSE
  86. #define STM32_I2C_USE_I2C2 FALSE
  87. #define STM32_I2C_BUSY_TIMEOUT 50
  88. #define STM32_I2C_I2C1_IRQ_PRIORITY 3
  89. #define STM32_I2C_I2C2_IRQ_PRIORITY 3
  90. #define STM32_I2C_USE_DMA TRUE
  91. #define STM32_I2C_I2C1_DMA_PRIORITY 1
  92. #define STM32_I2C_I2C2_DMA_PRIORITY 1
  93. #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  94. #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  95. #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  96. #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  97. #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
  98. /*
  99. * I2S driver system settings.
  100. */
  101. #define STM32_I2S_USE_SPI1 FALSE
  102. #define STM32_I2S_USE_SPI2 FALSE
  103. #define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
  104. STM32_I2S_MODE_RX)
  105. #define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
  106. STM32_I2S_MODE_RX)
  107. #define STM32_I2S_SPI1_IRQ_PRIORITY 2
  108. #define STM32_I2S_SPI2_IRQ_PRIORITY 2
  109. #define STM32_I2S_SPI1_DMA_PRIORITY 1
  110. #define STM32_I2S_SPI2_DMA_PRIORITY 1
  111. #define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  112. #define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  113. #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  114. #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  115. #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
  116. /*
  117. * ICU driver system settings.
  118. */
  119. #define STM32_ICU_USE_TIM1 FALSE
  120. #define STM32_ICU_USE_TIM2 FALSE
  121. #define STM32_ICU_USE_TIM3 FALSE
  122. #define STM32_ICU_TIM1_IRQ_PRIORITY 3
  123. #define STM32_ICU_TIM2_IRQ_PRIORITY 3
  124. #define STM32_ICU_TIM3_IRQ_PRIORITY 3
  125. /*
  126. * PWM driver system settings.
  127. */
  128. #define STM32_PWM_USE_ADVANCED FALSE
  129. #define STM32_PWM_USE_TIM1 FALSE
  130. #define STM32_PWM_USE_TIM2 FALSE
  131. #define STM32_PWM_USE_TIM3 FALSE
  132. #define STM32_PWM_TIM1_IRQ_PRIORITY 3
  133. #define STM32_PWM_TIM2_IRQ_PRIORITY 3
  134. #define STM32_PWM_TIM3_IRQ_PRIORITY 3
  135. /*
  136. * SERIAL driver system settings.
  137. */
  138. #define STM32_SERIAL_USE_USART1 TRUE
  139. #define STM32_SERIAL_USE_USART2 FALSE
  140. #define STM32_SERIAL_USART1_PRIORITY 3
  141. #define STM32_SERIAL_USART2_PRIORITY 3
  142. /*
  143. * SPI driver system settings.
  144. */
  145. #define STM32_SPI_USE_SPI1 FALSE
  146. #define STM32_SPI_USE_SPI2 FALSE
  147. #define STM32_SPI_SPI1_DMA_PRIORITY 1
  148. #define STM32_SPI_SPI2_DMA_PRIORITY 1
  149. #define STM32_SPI_SPI1_IRQ_PRIORITY 2
  150. #define STM32_SPI_SPI2_IRQ_PRIORITY 2
  151. #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  152. #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  153. #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  154. #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  155. #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
  156. /*
  157. * ST driver system settings.
  158. */
  159. #define STM32_ST_IRQ_PRIORITY 2
  160. #define STM32_ST_USE_TIMER 2
  161. /*
  162. * UART driver system settings.
  163. */
  164. #define STM32_UART_USE_USART1 FALSE
  165. #define STM32_UART_USE_USART2 FALSE
  166. #define STM32_UART_USART1_IRQ_PRIORITY 3
  167. #define STM32_UART_USART2_IRQ_PRIORITY 3
  168. #define STM32_UART_USART1_DMA_PRIORITY 0
  169. #define STM32_UART_USART2_DMA_PRIORITY 0
  170. #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
  171. #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
  172. #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
  173. #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
  174. #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
  175. /*
  176. * WDG driver system settings.
  177. */
  178. #define STM32_WDG_USE_IWDG FALSE
  179. #endif /* MCUCONF_H */