123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273 |
- #ifndef MCUCONF_H
- #define MCUCONF_H
- #define STM32F3xx_MCUCONF
- #define STM32F303_MCUCONF
- #define STM32_NO_INIT FALSE
- #define STM32_PVD_ENABLE FALSE
- #define STM32_PLS STM32_PLS_LEV0
- #define STM32_HSI_ENABLED TRUE
- #define STM32_LSI_ENABLED TRUE
- #define STM32_HSE_ENABLED TRUE
- #define STM32_LSE_ENABLED FALSE
- #define STM32_SW STM32_SW_PLL
- #define STM32_PLLSRC STM32_PLLSRC_HSE
- #define STM32_PREDIV_VALUE 1
- #define STM32_PLLMUL_VALUE 9
- #define STM32_HPRE STM32_HPRE_DIV1
- #define STM32_PPRE1 STM32_PPRE1_DIV2
- #define STM32_PPRE2 STM32_PPRE2_DIV2
- #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
- #define STM32_ADC12PRES STM32_ADC12PRES_DIV1
- #define STM32_ADC34PRES STM32_ADC34PRES_DIV1
- #define STM32_USART1SW STM32_USART1SW_PCLK
- #define STM32_USART2SW STM32_USART2SW_PCLK
- #define STM32_USART3SW STM32_USART3SW_PCLK
- #define STM32_UART4SW STM32_UART4SW_PCLK
- #define STM32_UART5SW STM32_UART5SW_PCLK
- #define STM32_I2C1SW STM32_I2C1SW_SYSCLK
- #define STM32_I2C2SW STM32_I2C2SW_SYSCLK
- #define STM32_TIM1SW STM32_TIM1SW_PCLK2
- #define STM32_TIM8SW STM32_TIM8SW_PCLK2
- #define STM32_RTCSEL STM32_RTCSEL_LSI
- #define STM32_USB_CLOCK_REQUIRED TRUE
- #define STM32_USBPRE STM32_USBPRE_DIV1P5
- #define STM32_IRQ_EXTI0_PRIORITY 6
- #define STM32_IRQ_EXTI1_PRIORITY 6
- #define STM32_IRQ_EXTI2_PRIORITY 6
- #define STM32_IRQ_EXTI3_PRIORITY 6
- #define STM32_IRQ_EXTI4_PRIORITY 6
- #define STM32_IRQ_EXTI5_9_PRIORITY 6
- #define STM32_IRQ_EXTI10_15_PRIORITY 6
- #define STM32_IRQ_EXTI16_PRIORITY 6
- #define STM32_IRQ_EXTI17_PRIORITY 6
- #define STM32_IRQ_EXTI18_PRIORITY 6
- #define STM32_IRQ_EXTI19_PRIORITY 6
- #define STM32_IRQ_EXTI20_PRIORITY 6
- #define STM32_IRQ_EXTI21_22_29_PRIORITY 6
- #define STM32_IRQ_EXTI30_32_PRIORITY 6
- #define STM32_IRQ_EXTI33_PRIORITY 6
- #define STM32_IRQ_TIM1_BRK_TIM15_PRIORITY 7
- #define STM32_IRQ_TIM1_UP_TIM16_PRIORITY 7
- #define STM32_IRQ_TIM1_TRGCO_TIM17_PRIORITY 7
- #define STM32_IRQ_TIM1_CC_PRIORITY 7
- #define STM32_ADC_DUAL_MODE FALSE
- #define STM32_ADC_COMPACT_SAMPLES FALSE
- #define STM32_ADC_USE_ADC1 FALSE
- #define STM32_ADC_USE_ADC2 FALSE
- #define STM32_ADC_USE_ADC3 FALSE
- #define STM32_ADC_USE_ADC4 FALSE
- #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
- #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
- #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
- #define STM32_ADC_ADC4_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
- #define STM32_ADC_ADC1_DMA_PRIORITY 2
- #define STM32_ADC_ADC2_DMA_PRIORITY 2
- #define STM32_ADC_ADC3_DMA_PRIORITY 2
- #define STM32_ADC_ADC4_DMA_PRIORITY 2
- #define STM32_ADC_ADC12_IRQ_PRIORITY 5
- #define STM32_ADC_ADC3_IRQ_PRIORITY 5
- #define STM32_ADC_ADC4_IRQ_PRIORITY 5
- #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
- #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
- #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
- #define STM32_ADC_ADC4_DMA_IRQ_PRIORITY 5
- #define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
- #define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
- #define STM32_CAN_USE_CAN1 FALSE
- #define STM32_CAN_CAN1_IRQ_PRIORITY 11
- #define STM32_DAC_DUAL_MODE FALSE
- #define STM32_DAC_USE_DAC1_CH1 TRUE
- #define STM32_DAC_USE_DAC1_CH2 TRUE
- #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
- #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
- #define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
- #define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
- #define STM32_GPT_USE_TIM1 FALSE
- #define STM32_GPT_USE_TIM2 FALSE
- #define STM32_GPT_USE_TIM3 FALSE
- #define STM32_GPT_USE_TIM4 FALSE
- #define STM32_GPT_USE_TIM6 FALSE
- #define STM32_GPT_USE_TIM7 FALSE
- #define STM32_GPT_USE_TIM8 FALSE
- #define STM32_GPT_USE_TIM15 FALSE
- #define STM32_GPT_USE_TIM16 FALSE
- #define STM32_GPT_USE_TIM17 FALSE
- #define STM32_GPT_TIM1_IRQ_PRIORITY 7
- #define STM32_GPT_TIM2_IRQ_PRIORITY 7
- #define STM32_GPT_TIM3_IRQ_PRIORITY 7
- #define STM32_GPT_TIM4_IRQ_PRIORITY 7
- #define STM32_GPT_TIM6_IRQ_PRIORITY 7
- #define STM32_GPT_TIM7_IRQ_PRIORITY 7
- #define STM32_GPT_TIM8_IRQ_PRIORITY 7
- #define STM32_I2C_USE_I2C1 FALSE
- #define STM32_I2C_USE_I2C2 FALSE
- #define STM32_I2C_BUSY_TIMEOUT 50
- #define STM32_I2C_I2C1_IRQ_PRIORITY 10
- #define STM32_I2C_I2C2_IRQ_PRIORITY 10
- #define STM32_I2C_USE_DMA TRUE
- #define STM32_I2C_I2C1_DMA_PRIORITY 1
- #define STM32_I2C_I2C2_DMA_PRIORITY 1
- #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
- #define STM32_ICU_USE_TIM1 TRUE
- #define STM32_ICU_USE_TIM2 FALSE
- #define STM32_ICU_USE_TIM3 TRUE
- #define STM32_ICU_USE_TIM4 FALSE
- #define STM32_ICU_USE_TIM8 TRUE
- #define STM32_ICU_USE_TIM15 FALSE
- #define STM32_ICU_TIM1_IRQ_PRIORITY 7
- #define STM32_ICU_TIM2_IRQ_PRIORITY 7
- #define STM32_ICU_TIM3_IRQ_PRIORITY 7
- #define STM32_ICU_TIM4_IRQ_PRIORITY 7
- #define STM32_ICU_TIM8_IRQ_PRIORITY 7
- #define STM32_PWM_USE_ADVANCED FALSE
- #define STM32_PWM_USE_TIM1 FALSE
- #define STM32_PWM_USE_TIM2 FALSE
- #define STM32_PWM_USE_TIM3 FALSE
- #define STM32_PWM_USE_TIM4 TRUE
- #define STM32_PWM_USE_TIM8 FALSE
- #define STM32_PWM_USE_TIM15 FALSE
- #define STM32_PWM_USE_TIM16 FALSE
- #define STM32_PWM_USE_TIM17 FALSE
- #define STM32_PWM_TIM1_IRQ_PRIORITY 7
- #define STM32_PWM_TIM2_IRQ_PRIORITY 7
- #define STM32_PWM_TIM3_IRQ_PRIORITY 7
- #define STM32_PWM_TIM4_IRQ_PRIORITY 7
- #define STM32_PWM_TIM8_IRQ_PRIORITY 7
- #define STM32_RTC_PRESA_VALUE 32
- #define STM32_RTC_PRESS_VALUE 1024
- #define STM32_RTC_CR_INIT 0
- #define STM32_RTC_TAMPCR_INIT 0
- #define STM32_SERIAL_USE_USART1 FALSE
- #define STM32_SERIAL_USE_USART2 FALSE
- #define STM32_SERIAL_USE_USART3 FALSE
- #define STM32_SERIAL_USE_UART4 FALSE
- #define STM32_SERIAL_USE_UART5 FALSE
- #define STM32_SERIAL_USART1_PRIORITY 12
- #define STM32_SERIAL_USART2_PRIORITY 12
- #define STM32_SERIAL_USART3_PRIORITY 12
- #define STM32_SERIAL_UART4_PRIORITY 12
- #define STM32_SERIAL_UART5_PRIORITY 12
- #define STM32_SPI_USE_SPI1 FALSE
- #define STM32_SPI_USE_SPI2 FALSE
- #define STM32_SPI_USE_SPI3 FALSE
- #define STM32_SPI_SPI1_DMA_PRIORITY 1
- #define STM32_SPI_SPI2_DMA_PRIORITY 1
- #define STM32_SPI_SPI3_DMA_PRIORITY 1
- #define STM32_SPI_SPI1_IRQ_PRIORITY 10
- #define STM32_SPI_SPI2_IRQ_PRIORITY 10
- #define STM32_SPI_SPI3_IRQ_PRIORITY 10
- #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
- #define STM32_ST_IRQ_PRIORITY 8
- #define STM32_ST_USE_TIMER 2
- #define STM32_UART_USE_USART1 FALSE
- #define STM32_UART_USE_USART2 FALSE
- #define STM32_UART_USE_USART3 FALSE
- #define STM32_UART_USART1_IRQ_PRIORITY 12
- #define STM32_UART_USART2_IRQ_PRIORITY 12
- #define STM32_UART_USART3_IRQ_PRIORITY 12
- #define STM32_UART_USART1_DMA_PRIORITY 0
- #define STM32_UART_USART2_DMA_PRIORITY 0
- #define STM32_UART_USART3_DMA_PRIORITY 0
- #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
- #define STM32_USB_USE_USB1 FALSE
- #define STM32_USB_LOW_POWER_ON_SUSPEND FALSE
- #define STM32_USB_USB1_HP_IRQ_PRIORITY 13
- #define STM32_USB_USB1_LP_IRQ_PRIORITY 14
- #define STM32_WDG_USE_IWDG FALSE
- #endif
|