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- #ifndef MCUCONF_H
- #define MCUCONF_H
- #define STM32F0xx_MCUCONF
- #define STM32_NO_INIT FALSE
- #define STM32_PVD_ENABLE FALSE
- #define STM32_PLS STM32_PLS_LEV0
- #define STM32_HSI_ENABLED TRUE
- #define STM32_HSI14_ENABLED TRUE
- #define STM32_LSI_ENABLED TRUE
- #define STM32_HSE_ENABLED FALSE
- #define STM32_LSE_ENABLED FALSE
- #define STM32_SW STM32_SW_PLL
- #define STM32_PLLSRC STM32_PLLSRC_HSI_DIV2
- #define STM32_PREDIV_VALUE 1
- #define STM32_PLLMUL_VALUE 12
- #define STM32_HPRE STM32_HPRE_DIV1
- #define STM32_PPRE STM32_PPRE_DIV1
- #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
- #define STM32_MCOPRE STM32_MCOPRE_DIV1
- #define STM32_PLLNODIV STM32_PLLNODIV_DIV2
- #define STM32_USBSW STM32_USBSW_HSI48
- #define STM32_CECSW STM32_CECSW_HSI
- #define STM32_I2C1SW STM32_I2C1SW_HSI
- #define STM32_USART1SW STM32_USART1SW_PCLK
- #define STM32_RTCSEL STM32_RTCSEL_LSI
- #define STM32_IRQ_EXTI0_1_IRQ_PRIORITY 3
- #define STM32_IRQ_EXTI2_3_IRQ_PRIORITY 3
- #define STM32_IRQ_EXTI4_15_IRQ_PRIORITY 3
- #define STM32_IRQ_EXTI16_IRQ_PRIORITY 3
- #define STM32_IRQ_EXTI17_20_IRQ_PRIORITY 3
- #define STM32_IRQ_EXTI21_22_IRQ_PRIORITY 3
- #define STM32_ADC_USE_ADC1 FALSE
- #define STM32_ADC_ADC1_CKMODE STM32_ADC_CKMODE_ADCCLK
- #define STM32_ADC_ADC1_DMA_PRIORITY 2
- #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
- #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
- #define STM32_GPT_USE_TIM1 FALSE
- #define STM32_GPT_USE_TIM2 FALSE
- #define STM32_GPT_USE_TIM3 FALSE
- #define STM32_GPT_USE_TIM14 FALSE
- #define STM32_GPT_TIM1_IRQ_PRIORITY 2
- #define STM32_GPT_TIM2_IRQ_PRIORITY 2
- #define STM32_GPT_TIM3_IRQ_PRIORITY 2
- #define STM32_GPT_TIM14_IRQ_PRIORITY 2
- #define STM32_I2C_USE_I2C1 FALSE
- #define STM32_I2C_USE_I2C2 FALSE
- #define STM32_I2C_BUSY_TIMEOUT 50
- #define STM32_I2C_I2C1_IRQ_PRIORITY 3
- #define STM32_I2C_I2C2_IRQ_PRIORITY 3
- #define STM32_I2C_USE_DMA TRUE
- #define STM32_I2C_I2C1_DMA_PRIORITY 1
- #define STM32_I2C_I2C2_DMA_PRIORITY 1
- #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
- #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
- #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
- #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
- #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
- #define STM32_I2S_USE_SPI1 FALSE
- #define STM32_I2S_USE_SPI2 FALSE
- #define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \
- STM32_I2S_MODE_RX)
- #define STM32_I2S_SPI2_MODE (STM32_I2S_MODE_MASTER | \
- STM32_I2S_MODE_RX)
- #define STM32_I2S_SPI1_IRQ_PRIORITY 2
- #define STM32_I2S_SPI2_IRQ_PRIORITY 2
- #define STM32_I2S_SPI1_DMA_PRIORITY 1
- #define STM32_I2S_SPI2_DMA_PRIORITY 1
- #define STM32_I2S_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
- #define STM32_I2S_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
- #define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
- #define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
- #define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure")
- #define STM32_ICU_USE_TIM1 FALSE
- #define STM32_ICU_USE_TIM2 FALSE
- #define STM32_ICU_USE_TIM3 TRUE
- #define STM32_ICU_TIM1_IRQ_PRIORITY 3
- #define STM32_ICU_TIM2_IRQ_PRIORITY 3
- #define STM32_ICU_TIM3_IRQ_PRIORITY 3
- #define STM32_PWM_USE_ADVANCED FALSE
- #define STM32_PWM_USE_TIM1 TRUE
- #define STM32_PWM_USE_TIM2 FALSE
- #define STM32_PWM_USE_TIM3 FALSE
- #define STM32_PWM_TIM1_IRQ_PRIORITY 3
- #define STM32_PWM_TIM2_IRQ_PRIORITY 3
- #define STM32_PWM_TIM3_IRQ_PRIORITY 3
- #define STM32_SERIAL_USE_USART1 FALSE
- #define STM32_SERIAL_USE_USART2 FALSE
- #define STM32_SERIAL_USART1_PRIORITY 3
- #define STM32_SERIAL_USART2_PRIORITY 3
- #define STM32_SPI_USE_SPI1 FALSE
- #define STM32_SPI_USE_SPI2 FALSE
- #define STM32_SPI_SPI1_DMA_PRIORITY 1
- #define STM32_SPI_SPI2_DMA_PRIORITY 1
- #define STM32_SPI_SPI1_IRQ_PRIORITY 2
- #define STM32_SPI_SPI2_IRQ_PRIORITY 2
- #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
- #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
- #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
- #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
- #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
- #define STM32_ST_IRQ_PRIORITY 2
- #define STM32_ST_USE_TIMER 2
- #define STM32_UART_USE_USART1 FALSE
- #define STM32_UART_USE_USART2 FALSE
- #define STM32_UART_USART1_IRQ_PRIORITY 3
- #define STM32_UART_USART2_IRQ_PRIORITY 3
- #define STM32_UART_USART1_DMA_PRIORITY 0
- #define STM32_UART_USART2_DMA_PRIORITY 0
- #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
- #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
- #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
- #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
- #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
- #define STM32_WDG_USE_IWDG FALSE
- #endif
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