stm32f1_mcuconf.h 5.6 KB

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  1. /*
  2. ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
  3. Licensed under the Apache License, Version 2.0 (the "License");
  4. you may not use this file except in compliance with the License.
  5. You may obtain a copy of the License at
  6. http://www.apache.org/licenses/LICENSE-2.0
  7. Unless required by applicable law or agreed to in writing, software
  8. distributed under the License is distributed on an "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  10. See the License for the specific language governing permissions and
  11. limitations under the License.
  12. */
  13. #pragma once
  14. /*
  15. * STM32F103 drivers configuration.
  16. * The following settings override the default settings present in
  17. * the various device driver implementation headers.
  18. * Note that the settings for each driver only have effect if the whole
  19. * driver is enabled in halconf.h.
  20. *
  21. * IRQ priorities:
  22. * 15...0 Lowest...Highest.
  23. *
  24. * DMA priorities:
  25. * 0...3 Lowest...Highest.
  26. */
  27. /*
  28. * HAL driver system settings.
  29. */
  30. #define STM32_NO_INIT FALSE
  31. #define STM32_HSI_ENABLED TRUE
  32. #define STM32_LSI_ENABLED FALSE
  33. #define STM32_HSE_ENABLED TRUE
  34. #define STM32_LSE_ENABLED FALSE
  35. #if STM32_HSECLK == 8000000U
  36. #define STM32_SW STM32_SW_PLL
  37. #define STM32_PLLSRC STM32_PLLSRC_HSE
  38. #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
  39. #define STM32_PLLMUL_VALUE 9
  40. #define STM32_PPRE1 STM32_PPRE1_DIV2
  41. #define STM32_PPRE2 STM32_PPRE2_DIV2
  42. #define STM32_ADCPRE STM32_ADCPRE_DIV4
  43. #elif STM32_HSECLK == 24000000U
  44. #define STM32_SW STM32_SW_HSE
  45. #define STM32_PLLSRC STM32_PLLSRC_HSE
  46. #define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
  47. #define STM32_PLLMUL_VALUE 9
  48. #define STM32_PPRE1 STM32_PPRE1_DIV1
  49. #define STM32_PPRE2 STM32_PPRE2_DIV1
  50. #define STM32_ADCPRE STM32_ADCPRE_DIV2
  51. #else
  52. #error "Unsupported STM32F1xx clock frequency"
  53. #endif
  54. #ifndef STM32_HPRE
  55. #define STM32_HPRE STM32_HPRE_DIV1
  56. #endif
  57. #define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
  58. #define STM32_RTCSEL STM32_RTCSEL_HSEDIV
  59. #define STM32_PVD_ENABLE FALSE
  60. #define STM32_PLS STM32_PLS_LEV0
  61. /*
  62. * ADC driver system settings.
  63. */
  64. #define STM32_ADC_ADC1_DMA_PRIORITY 2
  65. #define STM32_ADC_ADC1_IRQ_PRIORITY 6
  66. /*
  67. * EXT driver system settings.
  68. */
  69. #define STM32_EXT_EXTI0_IRQ_PRIORITY 6
  70. #define STM32_EXT_EXTI1_IRQ_PRIORITY 6
  71. #define STM32_EXT_EXTI2_IRQ_PRIORITY 6
  72. #define STM32_EXT_EXTI3_IRQ_PRIORITY 6
  73. #define STM32_EXT_EXTI4_IRQ_PRIORITY 6
  74. #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
  75. #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
  76. #define STM32_EXT_EXTI16_IRQ_PRIORITY 6
  77. #define STM32_EXT_EXTI17_IRQ_PRIORITY 6
  78. #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
  79. #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
  80. /*
  81. * GPT driver system settings.
  82. */
  83. #define STM32_GPT_TIM1_IRQ_PRIORITY 7
  84. #define STM32_GPT_TIM2_IRQ_PRIORITY 7
  85. #define STM32_GPT_TIM3_IRQ_PRIORITY 7
  86. #define STM32_GPT_TIM4_IRQ_PRIORITY 7
  87. #define STM32_GPT_TIM5_IRQ_PRIORITY 7
  88. #define STM32_GPT_TIM8_IRQ_PRIORITY 7
  89. /*
  90. * I2C driver system settings.
  91. */
  92. #define STM32_I2C_BUSY_TIMEOUT 50
  93. #define STM32_I2C_I2C1_IRQ_PRIORITY 5
  94. #define STM32_I2C_I2C2_IRQ_PRIORITY 5
  95. #define STM32_I2C_I2C1_DMA_PRIORITY 3
  96. #define STM32_I2C_I2C2_DMA_PRIORITY 3
  97. #define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
  98. /*
  99. * ICU driver system settings.
  100. */
  101. #define STM32_ICU_TIM1_IRQ_PRIORITY 7
  102. #define STM32_ICU_TIM2_IRQ_PRIORITY 7
  103. #define STM32_ICU_TIM3_IRQ_PRIORITY 7
  104. #define STM32_ICU_TIM4_IRQ_PRIORITY 7
  105. #define STM32_ICU_TIM5_IRQ_PRIORITY 7
  106. #define STM32_ICU_TIM8_IRQ_PRIORITY 7
  107. /*
  108. * PWM driver system settings.
  109. */
  110. #define STM32_PWM_TIM1_IRQ_PRIORITY 7
  111. #define STM32_PWM_TIM2_IRQ_PRIORITY 7
  112. #define STM32_PWM_TIM3_IRQ_PRIORITY 7
  113. #define STM32_PWM_TIM4_IRQ_PRIORITY 7
  114. #define STM32_PWM_TIM5_IRQ_PRIORITY 7
  115. #define STM32_PWM_TIM8_IRQ_PRIORITY 7
  116. /*
  117. * RTC driver system settings.
  118. */
  119. #define STM32_RTC_IRQ_PRIORITY 15
  120. /*
  121. * SERIAL driver system settings.
  122. */
  123. #define STM32_SERIAL_USART1_PRIORITY 12
  124. #define STM32_SERIAL_USART2_PRIORITY 12
  125. #define STM32_SERIAL_USART3_PRIORITY 12
  126. /*
  127. * SPI driver system settings.
  128. */
  129. #define STM32_SPI_SPI1_DMA_PRIORITY 1
  130. #define STM32_SPI_SPI2_DMA_PRIORITY 1
  131. #define STM32_SPI_SPI1_IRQ_PRIORITY 10
  132. #define STM32_SPI_SPI2_IRQ_PRIORITY 10
  133. #define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
  134. /*
  135. * ST driver system settings.
  136. */
  137. #define STM32_ST_IRQ_PRIORITY 8
  138. #ifndef STM32_ST_USE_TIMER
  139. #define STM32_ST_USE_TIMER 2
  140. #endif
  141. /*
  142. * UART driver system settings.
  143. */
  144. #define STM32_UART_USART1_IRQ_PRIORITY 12
  145. #define STM32_UART_USART2_IRQ_PRIORITY 12
  146. #define STM32_UART_USART3_IRQ_PRIORITY 12
  147. #define STM32_UART_USART1_DMA_PRIORITY 0
  148. #define STM32_UART_USART2_DMA_PRIORITY 0
  149. #define STM32_UART_USART3_DMA_PRIORITY 0
  150. #define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
  151. /*
  152. * WDG driver system settings.
  153. */
  154. #define STM32_WDG_USE_IWDG FALSE