N3Drive_STM32F407ZETx.dbgconf 2.7 KB

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  1. // File: STM32F405_415_407_417_427_437_429_439.dbgconf
  2. // Version: 1.0.0
  3. // Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
  4. // refer to STM32F40x STM32F41x datasheets
  5. // refer to STM32F42x STM32F43x datasheets
  6. // <<< Use Configuration Wizard in Context Menu >>>
  7. // <h> Debug MCU configuration register (DBGMCU_CR)
  8. // <o.2> DBG_STANDBY <i> Debug Standby Mode
  9. // <o.1> DBG_STOP <i> Debug Stop Mode
  10. // <o.0> DBG_SLEEP <i> Debug Sleep Mode
  11. // </h>
  12. DbgMCU_CR = 0x00000007;
  13. // <h> Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
  14. // <i> Reserved bits must be kept at reset value
  15. // <o.26> DBG_CAN2_STOP <i> CAN2 stopped when core is halted
  16. // <o.25> DBG_CAN1_STOP <i> CAN2 stopped when core is halted
  17. // <o.23> DBG_I2C3_SMBUS_TIMEOUT <i> I2C3 SMBUS timeout mode stopped when core is halted
  18. // <o.22> DBG_I2C2_SMBUS_TIMEOUT <i> I2C2 SMBUS timeout mode stopped when core is halted
  19. // <o.21> DBG_I2C1_SMBUS_TIMEOUT <i> I2C1 SMBUS timeout mode stopped when core is halted
  20. // <o.12> DBG_IWDG_STOP <i> Independent watchdog stopped when core is halted
  21. // <o.11> DBG_WWDG_STOP <i> Window watchdog stopped when core is halted
  22. // <o.10> DBG_RTC_STOP <i> RTC stopped when core is halted
  23. // <o.8> DBG_TIM14_STOP <i> TIM14 counter stopped when core is halted
  24. // <o.7> DBG_TIM13_STOP <i> TIM13 counter stopped when core is halted
  25. // <o.6> DBG_TIM12_STOP <i> TIM12 counter stopped when core is halted
  26. // <o.5> DBG_TIM7_STOP <i> TIM7 counter stopped when core is halted
  27. // <o.4> DBG_TIM6_STOP <i> TIM6 counter stopped when core is halted
  28. // <o.3> DBG_TIM5_STOP <i> TIM5 counter stopped when core is halted
  29. // <o.2> DBG_TIM4_STOP <i> TIM4 counter stopped when core is halted
  30. // <o.1> DBG_TIM3_STOP <i> TIM3 counter stopped when core is halted
  31. // <o.0> DBG_TIM2_STOP <i> TIM2 counter stopped when core is halted
  32. // </h>
  33. DbgMCU_APB1_Fz = 0x00000000;
  34. // <h> Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
  35. // <i> Reserved bits must be kept at reset value
  36. // <o.18> DBG_TIM11_STOP <i> TIM11 counter stopped when core is halted
  37. // <o.17> DBG_TIM10_STOP <i> TIM10 counter stopped when core is halted
  38. // <o.16> DBG_TIM9_STOP <i> TIM9 counter stopped when core is halted
  39. // <o.1> DBG_TIM8_STOP <i> TIM8 counter stopped when core is halted
  40. // <o.0> DBG_TIM1_STOP <i> TIM1 counter stopped when core is halted
  41. // </h>
  42. DbgMCU_APB2_Fz = 0x00000000;
  43. // <<< end of configuration section >>>