DSP2803x_CpuTimers.c 3.6 KB

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  1. // TI File $Revision: /main/1 $
  2. // Checkin $Date: December 5, 2008 18:00:45 $
  3. //###########################################################################
  4. //
  5. // FILE: DSP2803x_CpuTimers.c
  6. //
  7. // TITLE: CPU 32-bit Timers Initialization & Support Functions.
  8. //
  9. // NOTES:
  10. //
  11. //###########################################################################
  12. // $TI Release: 2803x Header Files V1.01 $
  13. // $Release Date: April 30, 2009 $
  14. //###########################################################################
  15. #include "DSP2803x_Device.h" // Headerfile Include File
  16. #include "DSP2803x_Examples.h" // Examples Include File
  17. struct CPUTIMER_VARS CpuTimer0;
  18. struct CPUTIMER_VARS CpuTimer1;
  19. struct CPUTIMER_VARS CpuTimer2;
  20. //---------------------------------------------------------------------------
  21. // InitCpuTimers:
  22. //---------------------------------------------------------------------------
  23. // This function initializes all three CPU timers to a known state.
  24. //
  25. void InitCpuTimers(void)
  26. {
  27. // CPU Timer 0
  28. // Initialize address pointers to respective timer registers:
  29. CpuTimer0.RegsAddr = &CpuTimer0Regs;
  30. // Initialize timer period to maximum:
  31. CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
  32. // Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
  33. CpuTimer0Regs.TPR.all = 0;
  34. CpuTimer0Regs.TPRH.all = 0;
  35. // Make sure timer is stopped:
  36. CpuTimer0Regs.TCR.bit.TSS = 1;
  37. // Reload all counter register with period value:
  38. CpuTimer0Regs.TCR.bit.TRB = 1;
  39. // Reset interrupt counters:
  40. CpuTimer0.InterruptCount = 0;
  41. // Initialize address pointers to respective timer registers:
  42. CpuTimer1.RegsAddr = &CpuTimer1Regs;
  43. CpuTimer2.RegsAddr = &CpuTimer2Regs;
  44. // Initialize timer period to maximum:
  45. CpuTimer1Regs.PRD.all = 0xFFFFFFFF;
  46. CpuTimer2Regs.PRD.all = 0xFFFFFFFF;
  47. // Initialize pre-scale counter to divide by 1 (SYSCLKOUT):
  48. CpuTimer1Regs.TPR.all = 0;
  49. CpuTimer1Regs.TPRH.all = 0;
  50. CpuTimer2Regs.TPR.all = 0;
  51. CpuTimer2Regs.TPRH.all = 0;
  52. // Make sure timers are stopped:
  53. CpuTimer1Regs.TCR.bit.TSS = 1;
  54. CpuTimer2Regs.TCR.bit.TSS = 1;
  55. // Reload all counter register with period value:
  56. CpuTimer1Regs.TCR.bit.TRB = 1;
  57. CpuTimer2Regs.TCR.bit.TRB = 1;
  58. // Reset interrupt counters:
  59. CpuTimer1.InterruptCount = 0;
  60. CpuTimer2.InterruptCount = 0;
  61. }
  62. //---------------------------------------------------------------------------
  63. // ConfigCpuTimer:
  64. //---------------------------------------------------------------------------
  65. // This function initializes the selected timer to the period specified
  66. // by the "Freq" and "Period" parameters. The "Freq" is entered as "MHz"
  67. // and the period in "uSeconds". The timer is held in the stopped state
  68. // after configuration.
  69. //
  70. void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period)
  71. {
  72. Uint32 temp;
  73. // Initialize timer period:
  74. Timer->CPUFreqInMHz = Freq;
  75. Timer->PeriodInUSec = Period;
  76. temp = (long) (Freq * Period);
  77. Timer->RegsAddr->PRD.all = temp;
  78. // Set pre-scale counter to divide by 1 (SYSCLKOUT):
  79. Timer->RegsAddr->TPR.all = 0;
  80. Timer->RegsAddr->TPRH.all = 0;
  81. // Initialize timer control register:
  82. Timer->RegsAddr->TCR.bit.TSS = 1; // 1 = Stop timer, 0 = Start/Restart Timer
  83. Timer->RegsAddr->TCR.bit.TRB = 1; // 1 = reload timer
  84. Timer->RegsAddr->TCR.bit.SOFT = 1;
  85. Timer->RegsAddr->TCR.bit.FREE = 1; // Timer Free Run Disabled
  86. Timer->RegsAddr->TCR.bit.TIE = 1; // 0 = Disable/ 1 = Enable Timer Interrupt
  87. // Reset interrupt counter:
  88. Timer->InterruptCount = 0;
  89. }
  90. //===========================================================================
  91. // End of file.
  92. //===========================================================================